122 lines
4.0 KiB
ArmAsm
122 lines
4.0 KiB
ArmAsm
/*
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* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <toolchain.h>
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#include <linker/sections.h>
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#include <offsets_short.h>
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#include <arch/cpu.h>
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/* exports */
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GTEXT(z_arch_swap)
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GTEXT(z_thread_entry_wrapper)
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/* Use ABI name of registers for the sake of simplicity */
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/*
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* unsigned int z_arch_swap(unsigned int key)
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*
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* Always called with interrupts locked
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* key is stored in a0 register
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*/
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SECTION_FUNC(exception.other, z_arch_swap)
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/* Make a system call to perform context switch */
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#ifdef CONFIG_EXECUTION_BENCHMARKING
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addi sp, sp, -__z_arch_esf_t_SIZEOF
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RV_OP_STOREREG ra, __z_arch_esf_t_ra_OFFSET(sp)
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RV_OP_STOREREG gp, __z_arch_esf_t_gp_OFFSET(sp)
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RV_OP_STOREREG tp, __z_arch_esf_t_tp_OFFSET(sp)
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RV_OP_STOREREG t0, __z_arch_esf_t_t0_OFFSET(sp)
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RV_OP_STOREREG t1, __z_arch_esf_t_t1_OFFSET(sp)
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RV_OP_STOREREG t2, __z_arch_esf_t_t2_OFFSET(sp)
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RV_OP_STOREREG t3, __z_arch_esf_t_t3_OFFSET(sp)
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RV_OP_STOREREG t4, __z_arch_esf_t_t4_OFFSET(sp)
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RV_OP_STOREREG t5, __z_arch_esf_t_t5_OFFSET(sp)
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RV_OP_STOREREG t6, __z_arch_esf_t_t6_OFFSET(sp)
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RV_OP_STOREREG a0, __z_arch_esf_t_a0_OFFSET(sp)
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RV_OP_STOREREG a1, __z_arch_esf_t_a1_OFFSET(sp)
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RV_OP_STOREREG a2, __z_arch_esf_t_a2_OFFSET(sp)
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RV_OP_STOREREG a3, __z_arch_esf_t_a3_OFFSET(sp)
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RV_OP_STOREREG a4, __z_arch_esf_t_a4_OFFSET(sp)
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RV_OP_STOREREG a5, __z_arch_esf_t_a5_OFFSET(sp)
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RV_OP_STOREREG a6, __z_arch_esf_t_a6_OFFSET(sp)
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RV_OP_STOREREG a7, __z_arch_esf_t_a7_OFFSET(sp)
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call read_timer_start_of_swap
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RV_OP_LOADREG ra, __z_arch_esf_t_ra_OFFSET(sp)
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RV_OP_LOADREG gp, __z_arch_esf_t_gp_OFFSET(sp)
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RV_OP_LOADREG tp, __z_arch_esf_t_tp_OFFSET(sp)
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RV_OP_LOADREG t0, __z_arch_esf_t_t0_OFFSET(sp)
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RV_OP_LOADREG t1, __z_arch_esf_t_t1_OFFSET(sp)
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RV_OP_LOADREG t2, __z_arch_esf_t_t2_OFFSET(sp)
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RV_OP_LOADREG t3, __z_arch_esf_t_t3_OFFSET(sp)
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RV_OP_LOADREG t4, __z_arch_esf_t_t4_OFFSET(sp)
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RV_OP_LOADREG t5, __z_arch_esf_t_t5_OFFSET(sp)
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RV_OP_LOADREG t6, __z_arch_esf_t_t6_OFFSET(sp)
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RV_OP_LOADREG a0, __z_arch_esf_t_a0_OFFSET(sp)
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RV_OP_LOADREG a1, __z_arch_esf_t_a1_OFFSET(sp)
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RV_OP_LOADREG a2, __z_arch_esf_t_a2_OFFSET(sp)
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RV_OP_LOADREG a3, __z_arch_esf_t_a3_OFFSET(sp)
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RV_OP_LOADREG a4, __z_arch_esf_t_a4_OFFSET(sp)
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RV_OP_LOADREG a5, __z_arch_esf_t_a5_OFFSET(sp)
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RV_OP_LOADREG a6, __z_arch_esf_t_a6_OFFSET(sp)
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RV_OP_LOADREG a7, __z_arch_esf_t_a7_OFFSET(sp)
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/* Release stack space */
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addi sp, sp, __z_arch_esf_t_SIZEOF
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#endif
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ecall
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/*
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* when thread is rescheduled, unlock irq and return.
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* Restored register a0 contains IRQ lock state of thread.
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*
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* Prior to unlocking irq, load return value of
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* z_arch_swap to temp register t2 (from
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* _thread_offset_to_swap_return_value). Normally, it should be -EAGAIN,
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* unless someone has previously called z_arch_thread_return_value_set(..).
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*/
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la t0, _kernel
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/* Get pointer to _kernel.current */
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RV_OP_LOADREG t1, _kernel_offset_to_current(t0)
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/* Load return value of z_arch_swap function in temp register t2 */
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lw t2, _thread_offset_to_swap_return_value(t1)
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/*
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* Unlock irq, following IRQ lock state in a0 register.
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* Use atomic instruction csrrs to do so.
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*/
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andi a0, a0, SOC_MSTATUS_IEN
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csrrs t0, mstatus, a0
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/* Set value of return register a0 to value of register t2 */
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addi a0, t2, 0
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/* Return */
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jalr x0, ra
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/*
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* void z_thread_entry_wrapper(k_thread_entry_t, void *, void *, void *)
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*/
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SECTION_FUNC(TEXT, z_thread_entry_wrapper)
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/*
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* z_thread_entry_wrapper is called for every new thread upon the return
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* of z_arch_swap or ISR. Its address, as well as its input function
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* arguments thread_entry_t, void *, void *, void * are restored from
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* the thread stack (initialized via function _thread).
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* In this case, thread_entry_t, * void *, void * and void * are stored
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* in registers a0, a1, a2 and a3. These registers are used as arguments
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* to function z_thread_entry. Hence, just call z_thread_entry with
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* return address set to 0 to indicate a non-returning function call.
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*/
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jal x0, z_thread_entry
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