273 lines
7.2 KiB
C
273 lines
7.2 KiB
C
/*
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* Copyright (c) 2019 Centaur Analytics, Inc
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <watchdog.h>
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#include <soc.h>
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#include <errno.h>
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#include <assert.h>
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#include <clock_control/stm32_clock_control.h>
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#include <drivers/clock_control.h>
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#include "wdt_wwdg_stm32.h"
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#define WWDG_INTERNAL_DIVIDER 4096U
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#define WWDG_RESET_LIMIT WWDG_COUNTER_MIN
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#define WWDG_COUNTER_MIN 0x40
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#define WWDG_COUNTER_MAX 0x7f
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/* The timeout of the WWDG in milliseconds is calculated by the below formula:
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*
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* t_WWDG = 1000 * ((counter & 0x3F) + 1) / f_WWDG (ms)
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*
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* where:
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* - t_WWDG: WWDG timeout
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* - counter: a value in [0x40, 0x7F] representing the cycles before timeout.
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* Giving the counter a value below 0x40, will result in an
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* immediate system reset. A reset is produced when the counter
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* rolls over from 0x40 to 0x3F.
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* - f_WWDG: the frequency of the WWDG clock. This can be calculated by the
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* below formula:
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* f_WWDG = f_PCLK / (4096 * prescaler) (Hz)
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* where:
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* - f_PCLK: the clock frequency of the system
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* - 4096: the constant internal divider
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* - prescaler: the programmable divider with valid values of 1, 2, 4 or 8
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*
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* The minimum timeout is calculated with:
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* - counter = 0x40
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* - prescaler = 1
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* The maximim timeout is calculated with:
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* - counter = 0x7F
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* - prescaler = 8
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*
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* E.g. for f_PCLK = 2MHz
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* t_WWDG_min = 1000 * ((0x40 & 0x3F) + 1) / (2000000 / (4096 * 1))
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* = 2.048 ms
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* t_WWDG_max = 1000 * ((0x7F & 0x3F) + 1) / (2000000 / (4096 * 8))
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* = 1048.576 ms
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*/
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#define ABS_DIFF_UINT(a, b) ((a) > (b) ? (a) - (b) : (b) - (a))
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#define WWDG_TIMEOUT_ERROR_MARGIN (100 * USEC_PER_MSEC)
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#define IS_WWDG_TIMEOUT(__TIMEOUT_GOLDEN__, __TIMEOUT__) \
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(ABS_DIFF_UINT(__TIMEOUT_GOLDEN__, __TIMEOUT__) < \
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WWDG_TIMEOUT_ERROR_MARGIN)
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static void wwdg_stm32_irq_config(struct device *dev);
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static u32_t wwdg_stm32_get_pclk(struct device *dev)
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{
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struct device *clk = device_get_binding(STM32_CLOCK_CONTROL_NAME);
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const struct wwdg_stm32_config *cfg = WWDG_STM32_CFG(dev);
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u32_t pclk_rate;
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__ASSERT_NO_MSG(clk);
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clock_control_get_rate(clk, (clock_control_subsys_t *) &cfg->pclken,
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&pclk_rate);
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return pclk_rate;
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}
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/**
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* @brief Calculates the timeout in microseconds.
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*
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* @param dev Pointer to device structure.
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* @param prescaler The prescaler value.
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* @param counter The counter value.
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* @return The timeout calculated in microseconds.
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*/
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static u32_t wwdg_stm32_get_timeout(struct device *dev, u32_t prescaler,
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u32_t counter)
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{
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u32_t divider = WWDG_INTERNAL_DIVIDER * (1 << (prescaler >> 7));
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float f_wwdg = wwdg_stm32_get_pclk(dev) / divider;
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return USEC_PER_SEC * (((counter & 0x3F) + 1) / f_wwdg);
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}
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/**
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* @brief Calculates prescaler & counter values.
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*
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* @param dev Pointer to device structure.
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* @param timeout Timeout value in microseconds.
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* @param prescaler Pointer to prescaler value.
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* @param counter Pointer to counter value.
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*/
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static void wwdg_stm32_convert_timeout(struct device *dev, u32_t timeout,
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u32_t *prescaler,
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u32_t *counter)
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{
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u32_t clock_freq = wwdg_stm32_get_pclk(dev);
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u8_t divider = 0U;
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u8_t shift = 3U;
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/* Convert timeout to seconds. */
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float timeout_s = (float)timeout / USEC_PER_SEC;
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float wwdg_freq;
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*prescaler = 0;
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*counter = 0;
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for (divider = 8; divider >= 1; divider >>= 1) {
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wwdg_freq = ((float)clock_freq) / WWDG_INTERNAL_DIVIDER / divider;
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/* +1 to ceil the result, which may lose from truncation */
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*counter = (u32_t)(timeout_s * wwdg_freq + 1) - 1;
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*counter |= WWDG_RESET_LIMIT;
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*prescaler = shift << 7;
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if (*counter <= WWDG_COUNTER_MAX) {
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break;
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}
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shift--;
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}
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}
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static int wwdg_stm32_setup(struct device *dev, u8_t options)
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{
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WWDG_TypeDef *wwdg = WWDG_STM32_STRUCT(dev);
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/* Deactivate running when debugger is attached. */
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if (options & WDT_OPT_PAUSE_HALTED_BY_DBG) {
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#if defined(CONFIG_SOC_SERIES_STM32F0X)
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LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_DBGMCU);
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#elif defined(CONFIG_SOC_SERIES_STM32L0X)
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LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_DBGMCU);
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#endif
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LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG_STOP);
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}
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if (options & WDT_OPT_PAUSE_IN_SLEEP) {
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return -ENOTSUP;
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}
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/* Enable the WWDG */
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LL_WWDG_Enable(wwdg);
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return 0;
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}
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static int wwdg_stm32_disable(struct device *dev)
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{
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/* watchdog cannot be stopped once started unless SOC gets a reset */
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ARG_UNUSED(dev);
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return -EPERM;
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}
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static int wwdg_stm32_install_timeout(struct device *dev,
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const struct wdt_timeout_cfg *config)
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{
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struct wwdg_stm32_data *data = WWDG_STM32_DATA(dev);
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WWDG_TypeDef *wwdg = WWDG_STM32_STRUCT(dev);
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u32_t timeout = config->window.max * USEC_PER_MSEC;
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u32_t calculated_timeout;
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u32_t prescaler = 0U;
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u32_t counter = 0U;
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if (config->callback != NULL) {
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data->callback = config->callback;
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}
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wwdg_stm32_convert_timeout(dev, timeout, &prescaler, &counter);
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calculated_timeout = wwdg_stm32_get_timeout(dev, prescaler, counter);
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if (!(IS_WWDG_PRESCALER(prescaler) && IS_WWDG_COUNTER(counter) &&
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IS_WWDG_TIMEOUT(timeout, calculated_timeout))) {
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/* One of the parameters provided is invalid */
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return -EINVAL;
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}
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data->counter = counter;
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/* Configure WWDG */
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/* Set the programmable prescaler */
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LL_WWDG_SetPrescaler(wwdg, prescaler);
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/* Set window the same as the counter to be able to feed the WWDG almost
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* immediately
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*/
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LL_WWDG_SetWindow(wwdg, counter);
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LL_WWDG_SetCounter(wwdg, counter);
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return 0;
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}
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static int wwdg_stm32_feed(struct device *dev, int channel_id)
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{
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WWDG_TypeDef *wwdg = WWDG_STM32_STRUCT(dev);
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struct wwdg_stm32_data *data = WWDG_STM32_DATA(dev);
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ARG_UNUSED(channel_id);
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LL_WWDG_SetCounter(wwdg, data->counter);
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return 0;
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}
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void wwdg_stm32_isr(void *arg)
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{
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struct device *const dev = (struct device *)arg;
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struct wwdg_stm32_data *data = WWDG_STM32_DATA(dev);
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WWDG_TypeDef *wwdg = WWDG_STM32_STRUCT(dev);
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if (LL_WWDG_IsEnabledIT_EWKUP(wwdg)) {
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if (LL_WWDG_IsActiveFlag_EWKUP(wwdg)) {
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LL_WWDG_ClearFlag_EWKUP(wwdg);
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data->callback(dev, 0);
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}
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}
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}
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static const struct wdt_driver_api wwdg_stm32_api = {
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.setup = wwdg_stm32_setup,
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.disable = wwdg_stm32_disable,
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.install_timeout = wwdg_stm32_install_timeout,
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.feed = wwdg_stm32_feed,
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};
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static int wwdg_stm32_init(struct device *dev)
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{
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struct device *clk = device_get_binding(STM32_CLOCK_CONTROL_NAME);
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const struct wwdg_stm32_config *cfg = WWDG_STM32_CFG(dev);
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__ASSERT_NO_MSG(clk);
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clock_control_on(clk, (clock_control_subsys_t *) &cfg->pclken);
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wwdg_stm32_irq_config(dev);
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return 0;
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}
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static struct wwdg_stm32_data wwdg_stm32_dev_data = {
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.counter = WWDG_RESET_LIMIT,
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.callback = NULL
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};
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static struct wwdg_stm32_config wwdg_stm32_dev_config = {
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.pclken = {
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.enr = DT_WWDT_0_CLOCK_BITS,
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.bus = DT_WWDT_0_CLOCK_BUS
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},
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.Instance = (WWDG_TypeDef *)DT_WWDT_0_BASE_ADDRESS,
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};
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DEVICE_AND_API_INIT(wwdg_stm32, DT_WWDT_0_NAME,
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wwdg_stm32_init, &wwdg_stm32_dev_data, &wwdg_stm32_dev_config,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&wwdg_stm32_api);
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static void wwdg_stm32_irq_config(struct device *dev)
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{
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WWDG_TypeDef *wwdg = WWDG_STM32_STRUCT(dev);
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IRQ_CONNECT(DT_WWDT_0_IRQ, DT_WWDT_0_IRQ_PRI,
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wwdg_stm32_isr, DEVICE_GET(wwdg_stm32), 0);
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irq_enable(DT_WWDT_0_IRQ);
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LL_WWDG_EnableIT_EWKUP(wwdg);
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}
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