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https://github.com/zephyrproject-rtos/zephyr.git
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4f77c2ad53
Promote the private z_arch_* namespace, which specifies the interface between the core kernel and the architecture code, to a new top-level namespace named arch_*. This allows our documentation generation to create online documentation for this set of interfaces, and this set of interfaces is worth treating in a more formal way anyway. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
143 lines
3.7 KiB
C
143 lines
3.7 KiB
C
/*
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* Copyright (c) 2016 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <arch/cpu.h>
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#include <kernel_structs.h>
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#include <inttypes.h>
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#include <logging/log.h>
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LOG_MODULE_DECLARE(os);
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FUNC_NORETURN void z_nios2_fatal_error(unsigned int reason,
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const z_arch_esf_t *esf)
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{
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if (esf != NULL) {
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/* Subtract 4 from EA since we added 4 earlier so that the
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* faulting instruction isn't retried.
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*
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* TODO: Only caller-saved registers get saved upon exception
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* entry. We may want to introduce a config option to save and
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* dump all registers, at the expense of some stack space.
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*/
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LOG_ERR("Faulting instruction: 0x%08x", esf->instr - 4);
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LOG_ERR(" r1: 0x%08x r2: 0x%08x r3: 0x%08x r4: 0x%08x",
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esf->r1, esf->r2, esf->r3, esf->r4);
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LOG_ERR(" r5: 0x%08x r6: 0x%08x r7: 0x%08x r8: 0x%08x",
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esf->r5, esf->r6, esf->r7, esf->r8);
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LOG_ERR(" r9: 0x%08x r10: 0x%08x r11: 0x%08x r12: 0x%08x",
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esf->r9, esf->r10, esf->r11, esf->r12);
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LOG_ERR(" r13: 0x%08x r14: 0x%08x r15: 0x%08x ra: 0x%08x",
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esf->r13, esf->r14, esf->r15, esf->ra);
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LOG_ERR("estatus: %08x", esf->estatus);
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}
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z_fatal_error(reason, esf);
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CODE_UNREACHABLE;
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}
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#if defined(CONFIG_EXTRA_EXCEPTION_INFO) && \
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(defined(CONFIG_PRINTK) || defined(CONFIG_LOG)) \
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&& defined(ALT_CPU_HAS_EXTRA_EXCEPTION_INFO)
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static char *cause_str(u32_t cause_code)
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{
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switch (cause_code) {
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case 0:
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return "reset";
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case 1:
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return "processor-only reset request";
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case 2:
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return "interrupt";
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case 3:
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return "trap";
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case 4:
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return "unimplemented instruction";
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case 5:
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return "illegal instruction";
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case 6:
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return "misaligned data address";
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case 7:
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return "misaligned destination address";
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case 8:
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return "division error";
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case 9:
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return "supervisor-only instruction address";
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case 10:
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return "supervisor-only instruction";
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case 11:
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return "supervisor-only data address";
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case 12:
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return "TLB miss";
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case 13:
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return "TLB permission violation (execute)";
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case 14:
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return "TLB permission violation (read)";
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case 15:
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return "TLB permission violation (write)";
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case 16:
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return "MPU region violation (instruction)";
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case 17:
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return "MPU region violation (data)";
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case 18:
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return "ECC TLB error";
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case 19:
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return "ECC fetch error (instruction)";
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case 20:
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return "ECC register file error";
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case 21:
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return "ECC data error";
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case 22:
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return "ECC data cache writeback error";
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case 23:
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return "bus instruction fetch error";
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case 24:
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return "bus data region violation";
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default:
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return "unknown";
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}
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}
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#endif
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FUNC_NORETURN void _Fault(const z_arch_esf_t *esf)
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{
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#if defined(CONFIG_PRINTK) || defined(CONFIG_LOG)
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/* Unfortunately, completely unavailable on Nios II/e cores */
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#ifdef ALT_CPU_HAS_EXTRA_EXCEPTION_INFO
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u32_t exc_reg, badaddr_reg, eccftl;
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enum nios2_exception_cause cause;
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exc_reg = z_nios2_creg_read(NIOS2_CR_EXCEPTION);
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/* Bit 31 indicates potentially fatal ECC error */
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eccftl = (exc_reg & NIOS2_EXCEPTION_REG_ECCFTL_MASK) != 0U;
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/* Bits 2-6 contain the cause code */
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cause = (exc_reg & NIOS2_EXCEPTION_REG_CAUSE_MASK)
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>> NIOS2_EXCEPTION_REG_CAUSE_OFST;
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LOG_ERR("Exception cause: %d ECCFTL: 0x%x", cause, eccftl);
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#if CONFIG_EXTRA_EXCEPTION_INFO
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LOG_ERR("reason: %s", cause_str(cause));
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#endif
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if (BIT(cause) & NIOS2_BADADDR_CAUSE_MASK) {
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badaddr_reg = z_nios2_creg_read(NIOS2_CR_BADADDR);
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LOG_ERR("Badaddr: 0x%x", badaddr_reg);
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}
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#endif /* ALT_CPU_HAS_EXTRA_EXCEPTION_INFO */
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#endif /* CONFIG_PRINTK || CONFIG_LOG */
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z_nios2_fatal_error(K_ERR_CPU_EXCEPTION, esf);
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}
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#ifdef ALT_CPU_HAS_DEBUG_STUB
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FUNC_NORETURN void arch_system_halt(unsigned int reason)
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{
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ARG_UNUSED(reason);
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z_nios2_break();
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CODE_UNREACHABLE;
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}
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#endif
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