79 lines
1.9 KiB
C
79 lines
1.9 KiB
C
/*
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* Copyright 2023 NXP
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*
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* Based on zephyr/soc/soc_legacy/arm/nxp_kinetis/ke1xf/soc.c, which is:
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* Copyright (c) 2019-2021 Vestas Wind Systems A/S
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <zephyr/sys/barrier.h>
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#include <cmsis_core.h>
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#include <OsIf.h>
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#if defined(CONFIG_HAS_MCUX_CACHE)
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#include <fsl_cache.h>
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#endif
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#if defined(CONFIG_WDOG_INIT)
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void z_arm_watchdog_init(void)
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{
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/*
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* NOTE: DO NOT SINGLE STEP THROUGH THIS SECTION!!! Watchdog
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* reconfiguration must take place within 128 bus clocks from
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* unlocking. Single stepping through the code will cause the
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* watchdog to close the unlock window again.
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*/
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if ((IP_WDOG->CS & WDOG_CS_CMD32EN_MASK) != 0U) {
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IP_WDOG->CNT = WDOG_UPDATE_KEY;
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} else {
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IP_WDOG->CNT = WDOG_UPDATE_KEY & 0xFFFFU;
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IP_WDOG->CNT = (WDOG_UPDATE_KEY >> 16U) & 0xFFFFU;
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}
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while (!(IP_WDOG->CS & WDOG_CS_ULK_MASK)) {
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;
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}
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IP_WDOG->TOVAL = 0xFFFFU;
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IP_WDOG->CS = (uint32_t) ((IP_WDOG->CS) & ~WDOG_CS_EN_MASK) | WDOG_CS_UPDATE_MASK;
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/* Wait for new configuration to take effect */
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while (!(IP_WDOG->CS & WDOG_CS_RCS_MASK)) {
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;
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}
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}
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#endif /* CONFIG_WDOG_INIT */
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static int soc_init(void)
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{
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#if !defined(CONFIG_ARM_MPU)
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uint32_t tmp;
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/*
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* Disable memory protection and clear slave port errors.
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* Note that the S32K1xx does not implement the optional Arm MPU but
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* instead the Soc includes its own NXP MPU module.
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*/
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tmp = IP_MPU->CESR;
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tmp &= ~MPU_CESR_VLD_MASK;
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tmp |= MPU_CESR_SPERR0_MASK | MPU_CESR_SPERR1_MASK
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| MPU_CESR_SPERR2_MASK | MPU_CESR_SPERR3_MASK;
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IP_MPU->CESR = tmp;
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#endif /* !CONFIG_ARM_MPU */
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#if defined(CONFIG_HAS_MCUX_CACHE) && defined(CONFIG_NXP_S32_ENABLE_CODE_CACHE)
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L1CACHE_EnableCodeCache();
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barrier_isync_fence_full();
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#endif
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OsIf_Init(NULL);
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return 0;
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}
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SYS_INIT(soc_init, PRE_KERNEL_1, 0);
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