125 lines
2.8 KiB
Plaintext
125 lines
2.8 KiB
Plaintext
# NXP S32K1XX MCUs series
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# Copyright 2023-2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_S32K1
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select ARM
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select HAS_NXP_S32_HAL
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select HAS_MCUX
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select CPU_HAS_NXP_MPU
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select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
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select MPU_ALLOW_FLASH_WRITE if !XIP
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select CLOCK_CONTROL
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select HAS_MCUX_LPUART
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select HAS_MCUX_LPI2C
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select HAS_MCUX_LPSPI
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select HAS_MCUX_FTM
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select HAS_MCUX_FLEXCAN
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select HAS_MCUX_WDOG32
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select HAS_MCUX_RTC
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config SOC_S32K116
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select CPU_CORTEX_M0PLUS
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config SOC_S32K118
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select CPU_CORTEX_M0PLUS
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config SOC_S32K142
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select CPU_CORTEX_M4
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select CPU_CORTEX_M_HAS_DWT
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select CPU_HAS_FPU
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select HAS_MCUX_CACHE
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config SOC_S32K142W
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select CPU_CORTEX_M4
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select CPU_CORTEX_M_HAS_DWT
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select CPU_HAS_FPU
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select HAS_MCUX_CACHE
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config SOC_S32K144
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select CPU_CORTEX_M4
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select CPU_CORTEX_M_HAS_DWT
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select CPU_HAS_FPU
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select HAS_MCUX_CACHE
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config SOC_S32K144W
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select CPU_CORTEX_M4
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select CPU_CORTEX_M_HAS_DWT
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select CPU_HAS_FPU
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select HAS_MCUX_CACHE
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config SOC_S32K146
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select CPU_CORTEX_M4
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select CPU_CORTEX_M_HAS_DWT
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select CPU_HAS_FPU
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select HAS_MCUX_CACHE
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config SOC_S32K148
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select CPU_CORTEX_M4
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select CPU_CORTEX_M_HAS_DWT
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select CPU_HAS_FPU
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select HAS_MCUX_CACHE
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if SOC_SERIES_S32K1
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config WDOG_INIT
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bool
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default y
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config NXP_S32_FLASH_CONFIG
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bool "NXP S32 flash configuration field"
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default y if XIP && !BOOTLOADER_MCUBOOT
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help
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Include the 16-byte flash configuration field that stores default
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protection settings (loaded on reset) and security information that
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allows the MCU to restrict access to the FTFx module.
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if NXP_S32_FLASH_CONFIG
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config NXP_S32_FLASH_CONFIG_OFFSET
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hex "NXP S32 flash configuration field offset"
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default 0x400
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config NXP_S32_FLASH_CONFIG_FSEC
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hex "Flash security byte (FSEC)"
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range 0 0xff
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default 0xfe
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help
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Configures the reset value of the FSEC register, which includes
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backdoor key access, mass erase, factory access, and flash security
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options.
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config NXP_S32_FLASH_CONFIG_FOPT
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hex "Flash nonvolatile option byte (FOPT)"
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range 0 0xff
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default 0xff
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help
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Configures the reset value of the FOPT register, which includes boot,
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NMI, and EzPort options.
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config NXP_S32_FLASH_CONFIG_FEPROT
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hex "EEPROM protection byte (FEPROT)"
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range 0 0xff
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default 0xff
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help
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Configures the reset value of the FEPROT register for FlexNVM
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devices. For program flash only devices, this byte is reserved.
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config NXP_S32_FLASH_CONFIG_FDPROT
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hex "Data flash protection byte (FDPROT)"
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range 0 0xff
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default 0xff
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help
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Configures the reset value of the FDPROT register for FlexNVM
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devices. For program flash only devices, this byte is reserved.
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endif # NXP_S32_FLASH_CONFIG
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config NXP_S32_ENABLE_CODE_CACHE
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bool "Code cache"
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default y
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depends on HAS_MCUX_CACHE
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endif # SOC_SERIES_S32K1
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