104 lines
3.3 KiB
ArmAsm
104 lines
3.3 KiB
ArmAsm
/*
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016 - 2019 , NXP
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* All rights reserved.
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*
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/toolchain.h>
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#include <zephyr/linker/sections.h>
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#include <zephyr/arch/cpu.h>
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#if defined(CONFIG_PLATFORM_SPECIFIC_INIT) && defined(CONFIG_SOC_LPC54114_M4)
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.syntax unified
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.arch armv7-m
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.text
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.thumb
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rel_vals:
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.long 0xE000ED00 /* cpu_id */
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.long 0x40000800 /* cpu_ctrl */
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.long 0x40000804 /* coproc_boot */
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.long 0x40000808 /* coproc_stack */
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.short 0x0FFF
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.short 0x0C24
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GTEXT(z_arm_platform_init)
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SECTION_FUNC(TEXT,z_arm_platform_init)
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/* Both the M0+ and M4 core come via this shared startup code,
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* but the M0+ and M4 core have different vector tables.
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* Determine if the core executing this code is the master or
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* the slave and handle each core state individually. */
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shared_boot_entry:
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ldr r6, =rel_vals
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/* Flag for slave core (0) */
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movs r4, 0
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movs r5, 1
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push {lr}
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bl SystemInit
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pop {lr}
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/* Determine which core (M0+ or M4) this code is running on */
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/* r2 = (((*cpu_id) >> 4) & 0xFFF); (M4 core == 0xC24) */
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get_current_core_id:
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ldr r0, [r6, #0]
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ldr r1, [r0] /* r1 = CPU ID status */
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lsrs r1, r1, #4 /* Right justify 12 CPU ID bits */
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ldrh r2, [r6, #16] /* Mask for CPU ID bits */
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ands r2, r1, r2 /* r2 = ARM COrtex CPU ID */
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ldrh r3, [r6, #18] /* Mask for CPU ID bits */
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cmp r3, r2 /* Core ID matches M4 identifier */
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bne get_master_status
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mov r4, r5 /* Set flag for master core (1) */
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/* Determine if M4 core is the master or slave */
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/* r3 = ((*cpu_ctrl) & 1); (0 == m0+, 1 == M4) */
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get_master_status:
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ldr r0, [r6, #4]
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ldr r3, [r0] /* r3 = SYSCON co-processor CPU control status */
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ands r3, r3, r5 /* r3 = (Bit 0: 1 = M4 is master, 0 = M4 is slave) */
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/* Select boot based on selected master core and core ID */
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select_boot:
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eors r3, r3, r4 /* r4 = (Bit 0: 0 = master, 1 = slave) */
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bne slave_boot
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b normal_boot
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/* Slave boot */
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slave_boot:
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ldr r0, [r6, #8]
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ldr r2, [r0] /* r1 = SYSCON co-processor boot address */
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cmp r2, #0 /* Slave boot address = 0 (not set up)? */
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beq cpu_sleep
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ldr r0, [r6, #12]
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ldr r1, [r0] /* r5 = SYSCON co-processor stack address */
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mov sp, r1 /* Update slave CPU stack pointer */
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/* Be sure to update VTOR for the slave MCU to point to the */
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/* slave vector table in boot memory */
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bx r2 /* Jump to slave boot address */
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/* Slave isn't yet setup for system boot from the master */
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/* so sleep until the master sets it up and then reboots it */
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cpu_sleep:
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mov sp, r5 /* Will force exception if something happens */
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cpu_sleep_wfi:
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wfi /* Sleep forever until master reboots */
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b cpu_sleep_wfi
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normal_boot:
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bx lr
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#endif
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