70 lines
1.8 KiB
Plaintext
70 lines
1.8 KiB
Plaintext
# LPC LPC54XXX MCU line
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# Copyright 2017, 2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_LPC54XXX
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select ARM
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select HAS_MCUX
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select HAS_MCUX_FLEXCOMM
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select HAS_MCUX_SYSCON
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select CPU_CORTEX_M_HAS_SYSTICK
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select PLATFORM_SPECIFIC_INIT
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config SOC_LPC54114_M4
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select CPU_CORTEX_M4
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select CPU_CORTEX_M_HAS_DWT
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select CPU_HAS_ARM_MPU
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select CPU_HAS_FPU
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select PLATFORM_SPECIFIC_INIT
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select CLOCK_CONTROL
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select HAS_MCUX_IAP_LEGACY
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config SOC_LPC54114_M0
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select CPU_CORTEX_M0PLUS
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select CPU_CORTEX_M_HAS_VTOR
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select CLOCK_CONTROL
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config MCUX_CORE_SUFFIX
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default "_cm4" if SOC_LPC54114_M4
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default "_cm0plus" if SOC_LPC54114_M0
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if SOC_SERIES_LPC54XXX
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config SECOND_CORE_MCUX
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bool "LPC54114 Cortex-M0 second core"
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help
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Driver for second core startup
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config SECOND_CORE_BOOT_ADDRESS_MCUX
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depends on SECOND_CORE_MCUX
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hex "Address the second core will boot at"
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default 0x20010000
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help
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This is the address the second core will boot from. Additionally this
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address is where we will copy the SECOND_IMAGE to. We default this to
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the base of SRAM1.
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# Workaround for not being able to have commas in macro arguments
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DT_CHOSEN_Z_CODE_CPU1_PARTITION := zephyr,code-cpu1-partition
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# Move the LMA address of second core into flash
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config BUILD_OUTPUT_ADJUST_LMA
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depends on SECOND_CORE_MCUX && SOC_LPC54114_M0
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default "-0x20010000+\
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$(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_CPU1_PARTITION))"
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config BUILD_OUTPUT_INFO_HEADER
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default y
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depends on SECOND_CORE_MCUX && SOC_LPC54114_M0
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config LPC54XXX_SRAM2_CLOCK
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bool "Clock LPC54XXX SRAM2"
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default y
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help
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SRAM2 ram bank is disabled out of reset. By default, CMSIS SystemInit
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will enable the clock to this RAM bank. Disable this Kconfig to leave
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this ram bank untouched out of reset.
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endif # SOC_SERIES_LPC54XXX
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