102 lines
2.4 KiB
C
102 lines
2.4 KiB
C
/*
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* Copyright (c) 2020, Seagate
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* Copyright 2022 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Board configuration macros for the nxp_lpc11u6x platform
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*
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* This header file is used to specify and describe board-level aspects for the
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* 'nxp_lpc11u6x' platform.
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*/
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#ifndef _SOC__H_
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#define _SOC__H_
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#ifndef _ASMLANGUAGE
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#include <zephyr/sys/util.h>
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#include <cmsis_core_m_defaults.h>
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#endif /* !_ASMLANGUAGE */
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/**
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* @brief Pin control register for standard digital I/O pins:
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*
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* [0:2] function.
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* [3:4] mode.
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* [5] hysteresis.
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* [6] invert input.
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* [7:9] reserved.
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* [10] open-drain mode.
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* [11:12] digital filter sample mode.
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* [13:15] clock divisor.
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* [16:31] reserved.
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*/
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#define IOCON_PIO_FUNC(x) (((x) & 0x7))
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#define IOCON_PIO_FUNC_MASK IOCON_PIO_FUNC(0x7)
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#define IOCON_PIO_MODE(x) (((x) & 0x3) << 3)
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#define IOCON_PIO_MODE_MASK IOCON_PIO_MODE(0x3)
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#define IOCON_PIO_HYS(x) (((x) & 0x1) << 5)
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#define IOCON_PIO_HYS_MASK IOCON_PIO_HYS(0x1)
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#define IOCON_PIO_INVERT(x) (((x) & 0x1) << 2)
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#define IOCON_PIO_INVERT_MASK IOCON_PIO_INVERT(0x1)
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#define IOCON_PIO_OD(x) (((x) & 0x1) << 10)
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#define IOCON_PIO_OD_MASK IOCON_PIO_OD(0x1)
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#define IOCON_PIO_SMODE(x) (((x) & 0x3) << 11)
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#define IOCON_PIO_SMODE_MASK IOCON_PIO_SMODE(0x3)
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#define IOCON_PIO_CLKDIV(x) (((x) & 0x7) << 13)
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#define IOCON_PIO_CLKDIV_MASK IOCON_PIO_CLKDIV(0x7)
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/**
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* @brief Control registers for digital/analog I/O pins:
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*
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* [0:2] function.
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* [3:4] mode.
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* [5] hysteresis.
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* [6] invert input.
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* [7] analog mode.
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* [8] input glitch filter.
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* [9] reserved.
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* [10] open-drain mode.
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* [11:12] digital filter sample mode.
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* [13:15] clock divisor.
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* [16:31] reserved.
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*/
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#define IOCON_PIO_ADMODE(x) (((x) & 0x1) << 7)
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#define IOCON_PIO_ADMODE_MASK IOCON_PIO_ADMODE(0x1)
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#define IOCON_PIO_FILTER(x) (((x) & 0x1) << 8)
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#define IOCON_PIO_FILTER_MASK IOCON_PIO_FILTER(0x1)
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/**
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* @brief Control registers for open-drain I/O pins (I2C):
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*
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* [0:2] function.
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* [3:7] reserved.
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* [8:9] I2C mode.
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* [10] reserved.
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* [11:12] digital filter sample mode.
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* [13:15] clock divisor.
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* [16:31] reserved.
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*/
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#define IOCON_PIO_I2CMODE(x) (((x) & 0x3) << 8)
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#define IOCON_PIO_I2CMODE_MASK IOCON_PIO_I2CMODE(0x3)
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#define IOCON_FUNC0 0
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#define IOCON_FUNC1 1
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#define IOCON_FUNC2 2
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#define IOCON_FUNC3 3
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#define IOCON_FUNC4 4
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#define IOCON_FUNC5 5
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#endif /* _SOC__H_ */
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