43 lines
839 B
C
43 lines
839 B
C
/*
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* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief interrupt management code for riscv SOCs supporting the riscv
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privileged architecture specification
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*/
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#include <zephyr/irq.h>
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#include <soc_common.h>
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void arch_irq_enable(unsigned int irq)
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{
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if (IS_ENABLED(CONFIG_HAS_ITE_INTC)) {
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ite_intc_irq_enable(irq);
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}
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}
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void arch_irq_disable(unsigned int irq)
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{
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if (IS_ENABLED(CONFIG_HAS_ITE_INTC)) {
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ite_intc_irq_disable(irq);
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}
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};
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int arch_irq_is_enabled(unsigned int irq)
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{
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/*
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* Return true from arch_irq_is_enabled() when external interrupt-enable
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* bit, and SOC's IER are both true.
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*/
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if (IS_ENABLED(CONFIG_HAS_ITE_INTC)) {
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return ((csr_read(mie) & BIT(IRQ_M_EXT)) &&
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ite_intc_irq_is_enable(irq));
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} else {
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return 0;
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}
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}
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