Kumar Gala de3d808280 dts/bindings: Add binding for riscv,cpu-intc ... The RISC-V CPU interrupt controller didn't have a binding. Add a simple one for it. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>		2019-06-21 07:52:12 -05:00
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arc	…
arm	dts: cleanup missing #{address,size}-cells	2019-06-20 22:48:57 -05:00
bindings	dts/bindings: Add binding for riscv,cpu-intc	2019-06-21 07:52:12 -05:00
common	…
nios2	…
posix	dts: posix: Add DTS support for POSIX architecture	2019-05-28 21:14:19 -04:00
riscv32	dts: cleanup missing #{address,size}-cells	2019-06-20 22:48:57 -05:00
x86	dts: Replace status = "ok" with status = "okay"	2019-06-14 19:51:13 -05:00
xtensa	dts: xtensa: Fix compatible for xtensa lx6	2019-06-16 10:07:29 -04:00
Kconfig	…