181 lines
5.0 KiB
C
181 lines
5.0 KiB
C
/*
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* Copyright (c) 2023 bytes at work AG
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* Copyright (c) 2020 Teslabs Engineering S.L.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_DISPLAY_DISPLAY_OTM8009A_H_
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#define ZEPHYR_DRIVERS_DISPLAY_DISPLAY_OTM8009A_H_
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/**
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* @name General parameters.
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* @{
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*/
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/** ID1 */
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#define OTM8009A_ID1 0x40U
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/** Read ID1 command */
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#define OTM8009A_CMD_ID1 0xDA
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/** Reset pulse time (ms), ref. Table 6.3.4.1 */
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#define OTM8009A_RESET_TIME 10U
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/** Wake up time after reset pulse, ref. Table 6.3.4.1 */
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#define OTM8009A_WAKE_TIME 20U
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/** Time to wait after exiting sleep mode (ms), ref. 5.2.11. */
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#define OTM8009A_EXIT_SLEEP_MODE_WAIT_TIME 5U
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/** @} */
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/**
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* @name Display timings (ref. table 6.4.2.1)
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* @{
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*/
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/** Horizontal low pulse width */
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#define OTM8009A_HSYNC 2U
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/** Horizontal front porch. */
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#define OTM8009A_HFP 34U
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/** Horizontal back porch. */
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#define OTM8009A_HBP 34U
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/** Vertical low pulse width. */
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#define OTM8009A_VSYNC 1U
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/** Vertical front porch. */
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#define OTM8009A_VFP 16U
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/** Vertical back porch. */
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#define OTM8009A_VBP 15U
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/** @} */
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/**
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* @name Register fields.
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* @{
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*/
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/**
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* @name MIPI DCS Write Control Display fields.
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* @{
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*/
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/** Write Control Display: brightness control. */
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#define OTM8009A_WRCTRLD_BCTRL BIT(5)
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/** Write Control Display: display dimming. */
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#define OTM8009A_WRCTRLD_DD BIT(3)
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/** Write Control Display: backlight. */
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#define OTM8009A_WRCTRLD_BL BIT(2)
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/** Adaptibe Brightness Control: off. */
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#define OTM8009A_WRCABC_OFF 0x00U
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/** Adaptibe Brightness Control: user interface. */
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#define OTM8009A_WRCABC_UI 0x01U
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/** Adaptibe Brightness Control: still picture. */
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#define OTM8009A_WRCABC_ST 0x02U
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/** Adaptibe Brightness Control: moving image. */
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#define OTM8009A_WRCABC_MV 0x03U
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/** @} */
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/**
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* @name MIPI MCS (Manufacturer Command Set).
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* @{
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*/
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/** Address Shift Function */
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#define OTM8009A_MCS_ADRSFT 0x0000U
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/** Panel Type Setting */
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#define OTM8009A_MCS_PANSET 0xB3A6U
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/* Source Driver Timing Setting */
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#define OTM8009A_MCS_SD_CTRL 0xC0A2U
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/** Panel Driving Mode */
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#define OTM8009A_MCS_P_DRV_M 0xC0B4U
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/** Oscillator Adjustment for Idle/Normal mode */
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#define OTM8009A_MCS_OSC_ADJ 0xC181U
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/** RGB Video Mode Setting */
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#define OTM8009A_MCS_RGB_VID_SET 0xC1A1U
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/** Source Driver Precharge Control */
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#define OTM8009A_MCS_SD_PCH_CTRL 0xC480U
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/** Command not documented */
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#define OTM8009A_MCS_NO_DOC1 0xC48AU
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/** Power Control Setting 1 */
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#define OTM8009A_MCS_PWR_CTRL1 0xC580U
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/** Power Control Setting 2 for Normal Mode */
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#define OTM8009A_MCS_PWR_CTRL2 0xC590U
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/** Power Control Setting 4 for DC Voltage */
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#define OTM8009A_MCS_PWR_CTRL4 0xC5B0U
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/** PWM Parameter 1 */
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#define OTM8009A_MCS_PWM_PARA1 0xC680U
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/** PWM Parameter 2 */
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#define OTM8009A_MCS_PWM_PARA2 0xC6B0U
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/** PWM Parameter 3 */
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#define OTM8009A_MCS_PWM_PARA3 0xC6B1U
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/** PWM Parameter 4 */
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#define OTM8009A_MCS_PWM_PARA4 0xC6B3U
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/** PWM Parameter 5 */
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#define OTM8009A_MCS_PWM_PARA5 0xC6B4U
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/** PWM Parameter 6 */
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#define OTM8009A_MCS_PWM_PARA6 0xC6B5U
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/** Panel Control Setting 1 */
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#define OTM8009A_MCS_PANCTRLSET1 0xCB80U
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/** Panel Control Setting 2 */
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#define OTM8009A_MCS_PANCTRLSET2 0xCB90U
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/** Panel Control Setting 3 */
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#define OTM8009A_MCS_PANCTRLSET3 0xCBA0U
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/** Panel Control Setting 4 */
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#define OTM8009A_MCS_PANCTRLSET4 0xCBB0U
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/** Panel Control Setting 5 */
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#define OTM8009A_MCS_PANCTRLSET5 0xCBC0U
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/** Panel Control Setting 6 */
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#define OTM8009A_MCS_PANCTRLSET6 0xCBD0U
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/** Panel Control Setting 7 */
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#define OTM8009A_MCS_PANCTRLSET7 0xCBE0U
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/** Panel Control Setting 8 */
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#define OTM8009A_MCS_PANCTRLSET8 0xCBF0U
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/** Panel U2D Setting 1 */
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#define OTM8009A_MCS_PANU2D1 0xCC80U
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/** Panel U2D Setting 2 */
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#define OTM8009A_MCS_PANU2D2 0xCC90U
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/** Panel U2D Setting 3 */
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#define OTM8009A_MCS_PANU2D3 0xCCA0U
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/** Panel D2U Setting 1 */
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#define OTM8009A_MCS_PAND2U1 0xCCB0U
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/** Panel D2U Setting 2 */
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#define OTM8009A_MCS_PAND2U2 0xCCC0U
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/** Panel D2U Setting 3 */
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#define OTM8009A_MCS_PAND2U3 0xCCD0U
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/** GOA VST Setting */
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#define OTM8009A_MCS_GOAVST 0xCE80U
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/** GOA CLKA1 Setting */
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#define OTM8009A_MCS_GOACLKA1 0xCEA0U
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/** GOA CLKA2 Setting */
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#define OTM8009A_MCS_GOACLKA2 0xCEA7U
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/** GOA CLKA3 Setting */
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#define OTM8009A_MCS_GOACLKA3 0xCEB0U
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/** GOA CLKA4 Setting */
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#define OTM8009A_MCS_GOACLKA4 0xCEB7U
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/** GOA ECLK Setting */
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#define OTM8009A_MCS_GOAECLK 0xCFC0U
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/** GOA Other Options 1 */
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#define OTM8009A_MCS_GOAPT1 0xCFC6U
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/** GOA Signal Toggle Option Setting */
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#define OTM8009A_MCS_GOATGOPT 0xCFC7U
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/** Command not documented */
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#define OTM8009A_MCS_NO_DOC2 0xCFD0U
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/** GVDD/NGVDD */
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#define OTM8009A_MCS_GVDDSET 0xD800U
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/** VCOM Voltage Setting */
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#define OTM8009A_MCS_VCOMDC 0xD900U
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/** Gamma Correction 2.2+ Setting */
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#define OTM8009A_MCS_GMCT2_2P 0xE100U
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/** Gamma Correction 2.2- Setting */
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#define OTM8009A_MCS_GMCT2_2N 0xE200U
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/** Command not documented */
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#define OTM8009A_MCS_NO_DOC3 0xF5B6U
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/** Enable Access Command2 "CMD2" */
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#define OTM8009A_MCS_CMD2_ENA1 0xFF00U
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/** Enable Access Orise Command2 */
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#define OTM8009A_MCS_CMD2_ENA2 0xFF80U
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/** @} */
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#endif /* ZEPHYR_DRIVERS_DISPLAY_DISPLAY_OTM8009A_H_ */
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