67 lines
2.0 KiB
C
67 lines
2.0 KiB
C
/*
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* Copyright (c) 2018 Foundries.io Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef SOC_RISCV32_OPENISA_RV32M1_SOC_RI5CY_H_
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#define SOC_RISCV32_OPENISA_RV32M1_SOC_RI5CY_H_
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/* Control and Status Registers (CSRs) available for RI5CY. */
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#define RI5CY_USTATUS 0x000
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#define RI5CY_UTVEC 0x005
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#define RI5CY_UHARTID 0x014
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#define RI5CY_UEPC 0x041
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#define RI5CY_UCAUSE 0x042
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#define RI5CY_MSTATUS 0x300
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#define RI5CY_MTVEC 0x305
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#define RI5CY_MEPC 0x341
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#define RI5CY_MCAUSE 0x342
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#define RI5CY_PCCR0 0x780
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#define RI5CY_PCCR1 0x781
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#define RI5CY_PCCR2 0x782
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#define RI5CY_PCCR3 0x783
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#define RI5CY_PCCR4 0x784
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#define RI5CY_PCCR5 0x785
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#define RI5CY_PCCR6 0x786
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#define RI5CY_PCCR7 0x787
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#define RI5CY_PCCR8 0x788
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#define RI5CY_PCCR9 0x789
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#define RI5CY_PCCR10 0x78A
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#define RI5CY_PCCR11 0x78B
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#define RI5CY_PCER 0x7A0
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#define RI5CY_PCMR 0x7A1
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#define RI5CY_LPSTART0 0x7B0
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#define RI5CY_LPEND0 0x7B1
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#define RI5CY_LPCOUNT0 0x7B2
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#define RI5CY_LPSTART1 0x7B4
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#define RI5CY_LPEND1 0x7B5
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#define RI5CY_LPCOUNT1 0x7B6
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#define RI5CY_PRIVLV 0xC10
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#define RI5CY_MHARTID 0xF14
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/*
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* Map from SoC-specific configuration to generic Zephyr macros.
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*
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* These are expected by the code in arch/, and must be provided for
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* the kernel to work (or even build at all).
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*
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* Some of these may also apply to ZERO-RISCY; needs investigation.
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*/
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/*
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* Exception code mask. Use of the bottom five bits is a subset of
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* what the standard allocates (which is XLEN-1 bits).
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*/
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#define SOC_MCAUSE_EXP_MASK 0x1F
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/*
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* Assembler instruction to exit from interrupt in machine mode.
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* The name "ERET" is a leftover from pre-v1.10 privileged ISA specs.
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* The "mret" mnemonic works properly with the Pulpino toolchain;
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* YMMV if using a generic toolchain.
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*/
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#define SOC_ERET mret
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/* The ecall exception number. This is a standard value. */
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#define SOC_MCAUSE_ECALL_EXP 11
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#endif /* SOC_RISCV32_OPENISA_RV32M1_SOC_RI5CY_H_ */
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