381 lines
8.6 KiB
C
381 lines
8.6 KiB
C
/*
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* Copyright (c) 2018, Cypress
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <device.h>
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#include <init.h>
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#include <arch/cpu.h>
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#include <arch/arm/aarch32/cortex_m/cmsis.h>
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#include "cy_syslib.h"
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#include "cy_gpio.h"
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#include "cy_scb_uart.h"
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#include "cy_syslib.h"
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#include "cy_syspm.h"
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#include "cy_sysclk.h"
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#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1
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#define CY_CFG_SYSCLK_FLL_ENABLED 1
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#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1
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#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL
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#define CY_CFG_SYSCLK_ILO_ENABLED 1
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#define CY_CFG_SYSCLK_IMO_ENABLED 1
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#define CY_CFG_SYSCLK_CLKLF_ENABLED 1
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#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1
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#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1
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#define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1
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#define CY_CFG_SYSCLK_CLKPATH3_ENABLED 1
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#define CY_CFG_SYSCLK_CLKPATH4_ENABLED 1
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#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1
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#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1
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#define CY_CFG_PWR_ENABLED 1
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#define CY_CFG_PWR_USING_LDO 1
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#define CY_CFG_PWR_USING_PMIC 0
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#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_1_1V
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#define CY_CFG_PWR_VDDA_MV 3300
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#define CY_CFG_PWR_USING_ULP 0
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static const cy_stc_fll_manual_config_t srss_0__clock_0__fll_0__fllConfig = {
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.fllMult = 500u,
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.refDiv = 20u,
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.ccoRange = CY_SYSCLK_FLL_CCO_RANGE4,
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.enableOutputDiv = true,
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.lockTolerance = 10u,
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.igain = 9u,
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.pgain = 5u,
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.settlingCount = 8u,
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.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
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.cco_Freq = 355u,
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};
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static inline void Cy_SysClk_ClkFastInit(void)
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{
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Cy_SysClk_ClkFastSetDivider(0u);
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}
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static inline void Cy_SysClk_FllInit(void)
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{
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Cy_SysClk_FllManualConfigure(&srss_0__clock_0__fll_0__fllConfig);
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Cy_SysClk_FllEnable(200000u);
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}
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static inline void Cy_SysClk_ClkHf0Init(void)
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{
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Cy_SysClk_ClkHfSetSource(0u, CY_SYSCLK_CLKHF_IN_CLKPATH0);
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Cy_SysClk_ClkHfSetDivider(0u, CY_SYSCLK_CLKHF_NO_DIVIDE);
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Cy_SysClk_ClkHfEnable(0u);
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}
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static inline void Cy_SysClk_IloInit(void)
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{
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Cy_SysClk_IloEnable();
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Cy_SysClk_IloHibernateOn(true);
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}
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static inline void Cy_SysClk_ClkLfInit(void)
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{
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Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ILO);
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}
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static inline void Cy_SysClk_ClkPath0Init(void)
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{
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Cy_SysClk_ClkPathSetSource(0u, CY_SYSCLK_CLKPATH_IN_IMO);
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}
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static inline void Cy_SysClk_ClkPath1Init(void)
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{
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Cy_SysClk_ClkPathSetSource(1u, CY_SYSCLK_CLKPATH_IN_IMO);
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}
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static inline void Cy_SysClk_ClkPath2Init(void)
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{
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Cy_SysClk_ClkPathSetSource(2u, CY_SYSCLK_CLKPATH_IN_IMO);
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}
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static inline void Cy_SysClk_ClkPath3Init(void)
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{
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Cy_SysClk_ClkPathSetSource(3u, CY_SYSCLK_CLKPATH_IN_IMO);
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}
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static inline void Cy_SysClk_ClkPath4Init(void)
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{
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Cy_SysClk_ClkPathSetSource(4u, CY_SYSCLK_CLKPATH_IN_IMO);
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}
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static inline void Cy_SysClk_ClkPeriInit(void)
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{
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Cy_SysClk_ClkPeriSetDivider(1u);
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}
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static inline void Cy_SysClk_ClkSlowInit(void)
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{
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Cy_SysClk_ClkSlowSetDivider(0u);
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}
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static void init_cycfg_platform(void)
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{
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/* Set worst case memory wait states (! ultra low power, 150 MHz), will
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* update at the end
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*/
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Cy_SysLib_SetWaitStates(false, 150);
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#ifdef CY_CFG_PWR_ENABLED
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/* Configure power mode */
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#if CY_CFG_PWR_USING_LDO
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Cy_SysPm_LdoSetVoltage(CY_CFG_PWR_LDO_VOLTAGE);
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#else
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Cy_SysPm_BuckEnable(CY_CFG_PWR_SIMO_VOLTAGE);
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#endif
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/* Configure PMIC */
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Cy_SysPm_UnlockPmic();
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#if CY_CFG_PWR_USING_PMIC
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Cy_SysPm_PmicEnableOutput();
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#else
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Cy_SysPm_PmicDisableOutput();
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#endif
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#endif
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/* Enable all source clocks */
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#ifdef CY_CFG_SYSCLK_PILO_ENABLED
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Cy_SysClk_PiloInit();
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#endif
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#ifdef CY_CFG_SYSCLK_WCO_ENABLED
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Cy_SysClk_WcoInit();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
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Cy_SysClk_ClkLfInit();
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#endif
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#ifdef CY_CFG_SYSCLK_ALTHF_ENABLED
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Cy_SysClk_AltHfInit();
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#endif
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#ifdef CY_CFG_SYSCLK_ECO_ENABLED
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Cy_SysClk_EcoInit();
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#endif
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#ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED
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Cy_SysClk_ExtClkInit();
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#endif
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/* Configure CPU clock dividers */
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#ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED
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Cy_SysClk_ClkFastInit();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED
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Cy_SysClk_ClkPeriInit();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED
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Cy_SysClk_ClkSlowInit();
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#endif
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/* Configure HF clocks */
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#ifdef CY_CFG_SYSCLK_CLKHF0_ENABLED
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Cy_SysClk_ClkHf0Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED
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Cy_SysClk_ClkHf1Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED
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Cy_SysClk_ClkHf2Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED
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Cy_SysClk_ClkHf3Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED
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Cy_SysClk_ClkHf4Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED
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Cy_SysClk_ClkHf5Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED
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Cy_SysClk_ClkHf6Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED
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Cy_SysClk_ClkHf7Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED
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Cy_SysClk_ClkHf8Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED
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Cy_SysClk_ClkHf9Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED
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Cy_SysClk_ClkHf10Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED
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Cy_SysClk_ClkHf11Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED
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Cy_SysClk_ClkHf12Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED
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Cy_SysClk_ClkHf13Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED
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Cy_SysClk_ClkHf14Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED
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Cy_SysClk_ClkHf15Init();
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#endif
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/* Configure Path Clocks */
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#ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED
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Cy_SysClk_ClkPath0Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
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Cy_SysClk_ClkPath1Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED
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Cy_SysClk_ClkPath2Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED
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Cy_SysClk_ClkPath3Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED
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Cy_SysClk_ClkPath4Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED
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Cy_SysClk_ClkPath5Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED
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Cy_SysClk_ClkPath6Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED
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Cy_SysClk_ClkPath7Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED
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Cy_SysClk_ClkPath8Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED
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Cy_SysClk_ClkPath9Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED
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Cy_SysClk_ClkPath10Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED
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Cy_SysClk_ClkPath11Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED
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Cy_SysClk_ClkPath12Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED
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Cy_SysClk_ClkPath13Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED
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Cy_SysClk_ClkPath14Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED
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Cy_SysClk_ClkPath15Init();
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#endif
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/* Configure and enable FLL */
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#ifdef CY_CFG_SYSCLK_FLL_ENABLED
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Cy_SysClk_FllInit();
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#endif
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/* Configure and enable PLLs */
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#ifdef CY_CFG_SYSCLK_PLL0_ENABLED
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Cy_SysClk_Pll0Init();
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#endif
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#ifdef CY_CFG_SYSCLK_PLL1_ENABLED
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Cy_SysClk_Pll1Init();
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#endif
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#ifdef CY_CFG_SYSCLK_PLL2_ENABLED
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Cy_SysClk_Pll2Init();
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#endif
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#ifdef CY_CFG_SYSCLK_PLL3_ENABLED
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Cy_SysClk_Pll3Init();
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#endif
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#ifdef CY_CFG_SYSCLK_PLL4_ENABLED
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Cy_SysClk_Pll4Init();
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#endif
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#ifdef CY_CFG_SYSCLK_PLL5_ENABLED
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Cy_SysClk_Pll5Init();
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#endif
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#ifdef CY_CFG_SYSCLK_PLL6_ENABLED
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Cy_SysClk_Pll6Init();
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#endif
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#ifdef CY_CFG_SYSCLK_PLL7_ENABLED
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Cy_SysClk_Pll7Init();
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#endif
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#ifdef CY_CFG_SYSCLK_PLL8_ENABLED
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Cy_SysClk_Pll8Init();
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#endif
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#ifdef CY_CFG_SYSCLK_PLL9_ENABLED
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Cy_SysClk_Pll9Init();
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#endif
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#ifdef CY_CFG_SYSCLK_PLL10_ENABLED
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Cy_SysClk_Pll10Init();
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#endif
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#ifdef CY_CFG_SYSCLK_PLL11_ENABLED
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Cy_SysClk_Pll11Init();
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#endif
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#ifdef CY_CFG_SYSCLK_PLL12_ENABLED
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Cy_SysClk_Pll12Init();
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#endif
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#ifdef CY_CFG_SYSCLK_PLL13_ENABLED
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Cy_SysClk_Pll13Init();
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#endif
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#ifdef CY_CFG_SYSCLK_PLL14_ENABLED
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Cy_SysClk_Pll14Init();
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#endif
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/* Configure miscellaneous clocks */
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#ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED
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Cy_SysClk_ClkTimerInit();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
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Cy_SysClk_ClkAltSysTickInit();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED
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Cy_SysClk_ClkPumpInit();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED
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Cy_SysClk_ClkBakInit();
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#endif
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/* Configure default enabled clocks */
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#ifdef CY_CFG_SYSCLK_ILO_ENABLED
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Cy_SysClk_IloInit();
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#else
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Cy_SysClk_IloDisable();
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#endif
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#ifndef CY_CFG_SYSCLK_IMO_ENABLED
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#error the IMO must be enabled for proper chip operation
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#endif
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/* Set accurate flash wait states */
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#if (defined(CY_CFG_PWR_ENABLED) && defined(CY_CFG_SYSCLK_CLKHF0_ENABLED))
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Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0,
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CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ);
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#endif
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}
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/**
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* Function Name: Cy_SystemInit
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*
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* \brief This function is called by the start-up code for the selected device.
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* It performs all of the necessary device configuration based on the design
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* settings. This includes settings for the platform resources and peripheral
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* clock.
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*
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*/
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void Cy_SystemInit(void)
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{
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/* Configure platform resources */
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init_cycfg_platform();
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/* Configure peripheral clocks */
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Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0u, 0u);
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Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0u);
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}
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static int init_cycfg_platform_wraper(struct device *arg)
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{
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ARG_UNUSED(arg);
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SystemInit();
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return 0;
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}
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SYS_INIT(init_cycfg_platform_wraper, PRE_KERNEL_1, 0);
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