69 lines
1.4 KiB
C
69 lines
1.4 KiB
C
/*
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* Copyright (c) 2019 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdbool.h>
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#include <drivers/pcie/pcie.h>
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#include <drivers/pcie/msi.h>
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/* functions documented in include/drivers/pcie/msi.h */
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u32_t pcie_get_cap(pcie_bdf_t bdf, u32_t cap_id)
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{
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u32_t reg = 0U;
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u32_t data;
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data = pcie_conf_read(bdf, PCIE_CONF_CMDSTAT);
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if (data & PCIE_CONF_CMDSTAT_CAPS) {
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data = pcie_conf_read(bdf, PCIE_CONF_CAPPTR);
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reg = PCIE_CONF_CAPPTR_FIRST(data);
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}
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while (reg) {
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data = pcie_conf_read(bdf, reg);
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if (PCIE_CONF_CAP_ID(data) == cap_id) {
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break;
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}
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reg = PCIE_CONF_CAP_NEXT(data);
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}
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return reg;
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}
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bool pcie_set_msi(pcie_bdf_t bdf, unsigned int irq)
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{
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bool success = false; /* keepin' the MISRA peeps employed */
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u32_t base;
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u32_t mcr;
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u32_t map;
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u32_t mdr;
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map = pcie_msi_map(irq);
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mdr = pcie_msi_mdr(irq);
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base = pcie_get_cap(bdf, PCIE_MSI_CAP_ID);
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if (base != 0U) {
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mcr = pcie_conf_read(bdf, base + PCIE_MSI_MCR);
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pcie_conf_write(bdf, base + PCIE_MSI_MAP0, map);
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if (mcr & PCIE_MSI_MCR_64) {
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pcie_conf_write(bdf, base + PCIE_MSI_MAP1_64, 0U);
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pcie_conf_write(bdf, base + PCIE_MSI_MDR_64, mdr);
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} else {
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pcie_conf_write(bdf, base + PCIE_MSI_MDR_32, mdr);
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}
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mcr |= PCIE_MSI_MCR_EN;
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mcr &= ~PCIE_MSI_MCR_MME; /* only 1 IRQ please */
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pcie_conf_write(bdf, base + PCIE_MSI_MCR, mcr);
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pcie_set_cmd(bdf, PCIE_CONF_CMDSTAT_MASTER, true);
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success = true;
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}
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return success;
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}
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