89 lines
3.0 KiB
C
89 lines
3.0 KiB
C
/*
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* Copyright (c) 2016, Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of the Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL CORPORATION OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "ss_power_states.h"
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/* Sensor Subsystem sleep operand definition.
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* Only a subset applies as internal sensor RTC
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* is not available.
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*
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* OP | Core | Timers | RTC
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* 000 | 0 | 1 | 1 <-- used for SS1
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* 001 | 0 | 0 | 1
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* 010 | 0 | 1 | 0
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* 011 | 0 | 0 | 0 <-- used for SS2
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* 100 | 0 | 0 | 0
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* 101 | 0 | 0 | 0
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* 110 | 0 | 0 | 0
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* 111 | 0 | 0 | 0
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*
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* sleep opcode argument:
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* - [7:5] : Sleep Operand
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* - [4] : Interrupt enable
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* - [3:0] : Interrupt threshold value
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*/
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#define QM_SS_SLEEP_MODE_CORE_OFF (0x0)
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#define QM_SS_SLEEP_MODE_CORE_OFF_TIMER_OFF (0x20)
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#define QM_SS_SLEEP_MODE_CORE_TIMERS_RTC_OFF (0x60)
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/* Enter SS1 :
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* SLEEP + sleep operand
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* __builtin_arc_sleep is not used here as it does not propagate sleep operand.
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*/
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void ss_power_cpu_ss1(const ss_power_cpu_ss1_mode_t mode)
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{
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/* Enter SS1 */
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switch (mode) {
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case SS_POWER_CPU_SS1_TIMER_OFF:
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__asm__ __volatile__(
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"sleep %0"
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:
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: "i"(QM_SS_SLEEP_MODE_CORE_OFF_TIMER_OFF));
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break;
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case SS_POWER_CPU_SS1_TIMER_ON:
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default:
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__asm__ __volatile__("sleep %0"
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:
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: "i"(QM_SS_SLEEP_MODE_CORE_OFF));
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break;
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}
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}
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/* Enter SS2 :
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* SLEEP + sleep operand
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* __builtin_arc_sleep is not used here as it does not propagate sleep operand.
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*/
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void ss_power_cpu_ss2(void)
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{
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/* Enter SS2 */
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__asm__ __volatile__("sleep %0"
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:
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: "i"(QM_SS_SLEEP_MODE_CORE_TIMERS_RTC_OFF));
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}
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