93 lines
3.2 KiB
C
93 lines
3.2 KiB
C
/*
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* Copyright (c) 2016, Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of the Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL CORPORATION OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "qm_ss_timer.h"
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static void (*callback[QM_SS_TIMER_NUM])(void *data);
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static void *callback_data[QM_SS_TIMER_NUM];
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static uint32_t qm_ss_timer_base[QM_SS_TIMER_NUM] = {QM_SS_TIMER_0_BASE};
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static __inline__ void qm_ss_timer_isr(qm_ss_timer_t timer)
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{
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uint32_t ctrl = 0;
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if (callback[timer]) {
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callback[timer](callback_data[timer]);
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}
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ctrl = __builtin_arc_lr(qm_ss_timer_base[timer] + QM_SS_TIMER_CONTROL);
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ctrl &= ~BIT(QM_SS_TIMER_CONTROL_INT_PENDING_OFFSET);
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__builtin_arc_sr(ctrl, qm_ss_timer_base[timer] + QM_SS_TIMER_CONTROL);
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}
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QM_ISR_DECLARE(qm_ss_timer_isr_0)
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{
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qm_ss_timer_isr(QM_SS_TIMER_0);
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}
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int qm_ss_timer_set_config(const qm_ss_timer_t timer,
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const qm_ss_timer_config_t *const cfg)
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{
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uint32_t ctrl = 0;
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QM_CHECK(cfg != NULL, -EINVAL);
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QM_CHECK(timer < QM_SS_TIMER_NUM, -EINVAL);
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ctrl = cfg->watchdog_mode << QM_SS_TIMER_CONTROL_WATCHDOG_OFFSET;
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ctrl |= cfg->inc_run_only << QM_SS_TIMER_CONTROL_NON_HALTED_OFFSET;
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ctrl |= cfg->int_en << QM_SS_TIMER_CONTROL_INT_EN_OFFSET;
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__builtin_arc_sr(ctrl, qm_ss_timer_base[timer] + QM_SS_TIMER_CONTROL);
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__builtin_arc_sr(cfg->count,
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qm_ss_timer_base[timer] + QM_SS_TIMER_LIMIT);
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callback[timer] = cfg->callback;
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callback_data[timer] = cfg->callback_data;
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return 0;
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}
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int qm_ss_timer_set(const qm_ss_timer_t timer, const uint32_t count)
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{
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QM_CHECK(timer < QM_SS_TIMER_NUM, -EINVAL);
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__builtin_arc_sr(count, qm_ss_timer_base[timer] + QM_SS_TIMER_COUNT);
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return 0;
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}
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int qm_ss_timer_get(const qm_ss_timer_t timer, uint32_t *const count)
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{
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QM_CHECK(timer < QM_SS_TIMER_NUM, -EINVAL);
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QM_CHECK(count != NULL, -EINVAL);
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*count = __builtin_arc_lr(qm_ss_timer_base[timer] + QM_SS_TIMER_COUNT);
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return 0;
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}
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