159 lines
4.9 KiB
C
159 lines
4.9 KiB
C
/*
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* Copyright (c) 2016, Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of the Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL CORPORATION OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "qm_ss_gpio.h"
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static void (*callback[QM_SS_GPIO_NUM])(void *data, uint32_t int_status);
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static void *callback_data[QM_SS_GPIO_NUM];
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static uint32_t gpio_base[QM_SS_GPIO_NUM] = {QM_SS_GPIO_0_BASE,
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QM_SS_GPIO_1_BASE};
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static void ss_gpio_isr_handler(qm_ss_gpio_t gpio)
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{
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uint32_t int_status = 0;
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uint32_t controller = gpio_base[gpio];
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int_status = __builtin_arc_lr(controller + QM_SS_GPIO_INTSTATUS);
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if (callback[gpio]) {
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callback[gpio](callback_data, int_status);
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}
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__builtin_arc_sr(int_status, controller + QM_SS_GPIO_PORTA_EOI);
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}
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QM_ISR_DECLARE(qm_ss_gpio_isr_0)
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{
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ss_gpio_isr_handler(QM_SS_GPIO_0);
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}
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QM_ISR_DECLARE(qm_ss_gpio_isr_1)
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{
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ss_gpio_isr_handler(QM_SS_GPIO_1);
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}
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int qm_ss_gpio_set_config(const qm_ss_gpio_t gpio,
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const qm_ss_gpio_port_config_t *const cfg)
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{
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uint32_t controller;
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QM_CHECK(gpio < QM_SS_GPIO_NUM, -EINVAL);
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QM_CHECK(cfg != NULL, -EINVAL);
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controller = gpio_base[gpio];
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__builtin_arc_sr(0xFFFFFFFF, controller + QM_SS_GPIO_INTMASK);
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__builtin_arc_sr(cfg->direction, controller + QM_SS_GPIO_SWPORTA_DDR);
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__builtin_arc_sr(cfg->int_type, controller + QM_SS_GPIO_INTTYPE_LEVEL);
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__builtin_arc_sr(cfg->int_polarity,
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controller + QM_SS_GPIO_INT_POLARITY);
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__builtin_arc_sr(cfg->int_debounce, controller + QM_SS_GPIO_DEBOUNCE);
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callback[gpio] = cfg->callback;
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callback_data[gpio] = cfg->callback_data;
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__builtin_arc_sr(cfg->int_en, controller + QM_SS_GPIO_INTEN);
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__builtin_arc_sr(~cfg->int_en, controller + QM_SS_GPIO_INTMASK);
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return 0;
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}
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int qm_ss_gpio_read_pin(const qm_ss_gpio_t gpio, const uint8_t pin,
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qm_ss_gpio_state_t *const state)
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{
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QM_CHECK(gpio < QM_SS_GPIO_NUM, -EINVAL);
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QM_CHECK(pin <= QM_SS_GPIO_NUM_PINS, -EINVAL);
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QM_CHECK(state != NULL, -EINVAL);
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*state =
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((__builtin_arc_lr(gpio_base[gpio] + QM_SS_GPIO_EXT_PORTA) >> pin) &
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1);
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return 0;
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}
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int qm_ss_gpio_set_pin(const qm_ss_gpio_t gpio, const uint8_t pin)
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{
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uint32_t val;
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QM_CHECK(gpio < QM_SS_GPIO_NUM, -EINVAL);
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QM_CHECK(pin <= QM_SS_GPIO_NUM_PINS, -EINVAL);
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val = __builtin_arc_lr(gpio_base[gpio] + QM_SS_GPIO_SWPORTA_DR) |
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BIT(pin);
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__builtin_arc_sr(val, gpio_base[gpio] + QM_SS_GPIO_SWPORTA_DR);
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return 0;
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}
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int qm_ss_gpio_clear_pin(const qm_ss_gpio_t gpio, const uint8_t pin)
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{
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uint32_t val;
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QM_CHECK(gpio < QM_SS_GPIO_NUM, -EINVAL);
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QM_CHECK(pin <= QM_SS_GPIO_NUM_PINS, -EINVAL);
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val = __builtin_arc_lr(gpio_base[gpio] + QM_SS_GPIO_SWPORTA_DR);
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val &= ~BIT(pin);
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__builtin_arc_sr(val, gpio_base[gpio] + QM_SS_GPIO_SWPORTA_DR);
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return 0;
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}
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int qm_ss_gpio_set_pin_state(const qm_ss_gpio_t gpio, const uint8_t pin,
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const qm_ss_gpio_state_t state)
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{
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uint32_t val;
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QM_CHECK(gpio < QM_SS_GPIO_NUM, -EINVAL);
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QM_CHECK(state < QM_SS_GPIO_STATE_NUM, -EINVAL);
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val = __builtin_arc_lr(gpio_base[gpio] + QM_SS_GPIO_SWPORTA_DR);
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val ^= (-state ^ val) & (1 << pin);
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__builtin_arc_sr(val, gpio_base[gpio] + QM_SS_GPIO_SWPORTA_DR);
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return 0;
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}
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int qm_ss_gpio_read_port(const qm_ss_gpio_t gpio, uint32_t *const port)
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{
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QM_CHECK(gpio < QM_SS_GPIO_NUM, -EINVAL);
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QM_CHECK(port != NULL, -EINVAL);
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*port = (__builtin_arc_lr(gpio_base[gpio] + QM_SS_GPIO_EXT_PORTA));
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return 0;
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}
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int qm_ss_gpio_write_port(const qm_ss_gpio_t gpio, const uint32_t val)
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{
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QM_CHECK(gpio < QM_SS_GPIO_NUM, -EINVAL);
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__builtin_arc_sr(val, gpio_base[gpio] + QM_SS_GPIO_SWPORTA_DR);
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return 0;
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}
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