61 lines
2.3 KiB
C
61 lines
2.3 KiB
C
/*
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* Copyright (c) 2016, Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of the Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL CORPORATION OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "rar.h"
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#if (HAS_RAR)
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int rar_set_mode(const rar_state_t mode)
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{
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QM_CHECK(mode <= RAR_RETENTION, -EINVAL);
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volatile uint32_t i = 32;
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volatile uint32_t reg;
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switch (mode) {
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case RAR_RETENTION:
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QM_SCSS_PMU->aon_vr |=
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(QM_AON_VR_PASS_CODE | QM_AON_VR_ROK_BUF_VREG_MASK);
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QM_SCSS_PMU->aon_vr |=
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(QM_AON_VR_PASS_CODE | QM_AON_VR_VREG_SEL);
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break;
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case RAR_NORMAL:
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reg = QM_SCSS_PMU->aon_vr & ~QM_AON_VR_VREG_SEL;
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QM_SCSS_PMU->aon_vr = QM_AON_VR_PASS_CODE | reg;
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/* Wait for >= 2usec, at most 64 clock cycles. */
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while (i--) {
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__asm__ __volatile__("nop");
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}
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reg = QM_SCSS_PMU->aon_vr & ~QM_AON_VR_ROK_BUF_VREG_MASK;
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QM_SCSS_PMU->aon_vr = QM_AON_VR_PASS_CODE | reg;
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break;
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}
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return 0;
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}
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#endif
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