131 lines
3.4 KiB
C
131 lines
3.4 KiB
C
/*
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* Copyright (c) 2016, Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of the Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL CORPORATION OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __MVIC_H__
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#define __MVIC_H__
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#include <stdint.h>
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#include "qm_common.h"
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#include "qm_soc_regs.h"
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#define NUM_IRQ_LINES (32)
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static uint32_t _mvic_get_irq_val(unsigned int irq)
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{
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/* Register Select - select which IRQ line we are configuring
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* Bits 0 and 4 are reserved
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* So, for IRQ 15 ( 0x01111 ) write 0x101110
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*/
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QM_IOAPIC->ioregsel.reg = ((irq & 0x7) << 1) | ((irq & 0x18) << 2);
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return QM_IOAPIC->iowin.reg;
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}
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static void _mvic_set_irq_val(unsigned int irq, uint32_t value)
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{
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/* Register Select - select which IRQ line we are configuring
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* Bits 0 and 4 are reserved
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* So, for IRQ 15 ( 0x01111 ) write 0x101110
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*/
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QM_IOAPIC->ioregsel.reg = ((irq & 0x7) << 1) | ((irq & 0x18) << 2);
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QM_IOAPIC->iowin.reg = value;
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}
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/**
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* Initialise MVIC.
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*/
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static __inline__ void mvic_init(void)
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{
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uint32_t i;
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for (i = 0; i < NUM_IRQ_LINES; i++) {
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/* Clear up any spurious LAPIC interrupts, each call only
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* clears one bit.
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*/
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QM_MVIC->eoi.reg = 0;
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/* Mask interrupt */
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_mvic_set_irq_val(i, BIT(16));
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}
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}
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/**
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* Register IRQ with MVIC.
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*
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* @param irq IRQ to register.
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*/
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static __inline__ void mvic_register_irq(uint32_t irq)
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{
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/* Set IRQ triggering scheme and unmask the line. */
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switch (irq) {
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case QM_IRQ_RTC_0:
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case QM_IRQ_AONPT_0:
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case QM_IRQ_PIC_TIMER:
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case QM_IRQ_WDT_0:
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/* positive edge */
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_mvic_set_irq_val(irq, 0);
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break;
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default:
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/* high level */
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_mvic_set_irq_val(irq, BIT(15));
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break;
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}
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}
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/**
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* Unmask IRQ with MVIC.
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*
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* @param irq IRQ to unmask.
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*/
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static __inline__ void mvic_unmask_irq(uint32_t irq)
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{
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uint32_t value = _mvic_get_irq_val(irq);
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value &= ~BIT(16);
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_mvic_set_irq_val(irq, value);
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}
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/**
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* Mask IRQ with MVIC.
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*
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* @param irq IRQ to mask.
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*/
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static __inline__ void mvic_mask_irq(uint32_t irq)
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{
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uint32_t value = _mvic_get_irq_val(irq);
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value |= BIT(16);
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_mvic_set_irq_val(irq, value);
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}
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#endif /* __MVIC_H__ */
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