124 lines
3.1 KiB
C
124 lines
3.1 KiB
C
/*
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* Copyright (c) 2017, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <init.h>
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#include <soc.h>
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#include "wdog_imx.h"
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/* Initialize clock. */
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void SOC_ClockInit(void)
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{
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/* OSC/PLL is already initialized by Cortex-A7 (u-boot) */
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/*
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* Disable WDOG3
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* Note : The WDOG clock Root is shared by all the 4 WDOGs,
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* so Zephyr code should avoid closing it
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*/
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CCM_UpdateRoot(CCM, ccmRootWdog, ccmRootmuxWdogOsc24m, 0, 0);
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CCM_EnableRoot(CCM, ccmRootWdog);
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CCM_ControlGate(CCM, ccmCcgrGateWdog3, ccmClockNeededRun);
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RDC_SetPdapAccess(RDC, rdcPdapWdog3,
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RDC_DOMAIN_PERM(CONFIG_DOMAIN_ID, RDC_DOMAIN_PERM_RW),
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false, false);
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WDOG_DisablePowerdown(WDOG3);
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CCM_ControlGate(CCM, ccmCcgrGateWdog3, ccmClockNotNeeded);
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/* We need system PLL Div2 to run M4 core */
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CCM_ControlGate(CCM, ccmPllGateSys, ccmClockNeededRun);
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CCM_ControlGate(CCM, ccmPllGateSysDiv2, ccmClockNeededRun);
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/* Enable clock gate for IP bridge and IO mux */
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CCM_ControlGate(CCM, ccmCcgrGateIpmux1, ccmClockNeededRun);
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CCM_ControlGate(CCM, ccmCcgrGateIpmux2, ccmClockNeededRun);
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CCM_ControlGate(CCM, ccmCcgrGateIpmux3, ccmClockNeededRun);
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CCM_ControlGate(CCM, ccmCcgrGateIomux, ccmClockNeededRun);
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CCM_ControlGate(CCM, ccmCcgrGateIomuxLpsr, ccmClockNeededRun);
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/* Enable clock gate for RDC */
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CCM_ControlGate(CCM, ccmCcgrGateRdc, ccmClockNeededRun);
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}
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void SOC_RdcInit(void)
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{
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/* Move M4 core to specific RDC domain */
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RDC_SetDomainID(RDC, rdcMdaM4, CONFIG_DOMAIN_ID, false);
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}
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#ifdef CONFIG_GPIO_IMX
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static void nxp_mcimx7_gpio_config(void)
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{
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#ifdef CONFIG_GPIO_IMX_PORT_1
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RDC_SetPdapAccess(RDC, rdcPdapGpio1,
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RDC_DOMAIN_PERM(CONFIG_DOMAIN_ID, RDC_DOMAIN_PERM_RW),
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false, false);
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/* Enable gpio clock gate */
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CCM_ControlGate(CCM, ccmCcgrGateGpio1, ccmClockNeededRunWait);
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#endif /* CONFIG_GPIO_IMX_PORT_1 */
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#ifdef CONFIG_GPIO_IMX_PORT_2
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RDC_SetPdapAccess(RDC, rdcPdapGpio2,
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RDC_DOMAIN_PERM(CONFIG_DOMAIN_ID, RDC_DOMAIN_PERM_RW),
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false, false);
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/* Enable gpio clock gate */
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CCM_ControlGate(CCM, ccmCcgrGateGpio2, ccmClockNeededRunWait);
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#endif /* CONFIG_GPIO_IMX_PORT_2 */
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}
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#endif /* CONFIG_GPIO_IMX */
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#ifdef CONFIG_UART_IMX
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static void nxp_mcimx7_uart_config(void)
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{
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#ifdef CONFIG_UART_IMX_UART_2
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/* We need to grasp board uart exclusively */
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RDC_SetPdapAccess(RDC, rdcPdapUart2,
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RDC_DOMAIN_PERM(CONFIG_DOMAIN_ID, RDC_DOMAIN_PERM_RW),
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false, false);
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/* Select clock derived from OSC clock(24M) */
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CCM_UpdateRoot(CCM, ccmRootUart2, ccmRootmuxUartOsc24m, 0, 0);
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/* Enable uart clock */
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CCM_EnableRoot(CCM, ccmRootUart2);
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/*
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* IC Limitation
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* M4 stop will cause A7 UART lose functionality
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* So we need UART clock all the time
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*/
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CCM_ControlGate(CCM, ccmCcgrGateUart2, ccmClockNeededAll);
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#endif /* #ifdef CONFIG_UART_IMX_UART_2 */
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}
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#endif /* CONFIG_UART_IMX */
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static int nxp_mcimx7_init(struct device *arg)
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{
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ARG_UNUSED(arg);
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/* SoC specific RDC settings */
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SOC_RdcInit();
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/* BoC specific clock settings */
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SOC_ClockInit();
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#ifdef CONFIG_GPIO_IMX
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nxp_mcimx7_gpio_config();
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#endif /* CONFIG_GPIO_IMX */
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#ifdef CONFIG_UART_IMX
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nxp_mcimx7_uart_config();
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#endif /* CONFIG_UART_IMX */
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return 0;
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}
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SYS_INIT(nxp_mcimx7_init, PRE_KERNEL_1, 0);
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