142 lines
3.6 KiB
C
142 lines
3.6 KiB
C
/*
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* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief RISCV32 specific kernel interface header
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* This header contains the RISCV32 specific kernel interface. It is
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* included by the generic kernel interface header (arch/cpu.h)
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*/
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#ifndef _RISCV32_ARCH_H_
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#define _RISCV32_ARCH_H_
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#include "exp.h"
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#include "sys_io.h"
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#include <irq.h>
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#include <sw_isr_table.h>
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#include <soc.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* stacks, for RISCV architecture stack should be 16byte-aligned */
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#define STACK_ALIGN 16
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#ifndef _ASMLANGUAGE
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#include <misc/util.h>
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#define STACK_ROUND_UP(x) ROUND_UP(x, STACK_ALIGN)
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#define STACK_ROUND_DOWN(x) ROUND_DOWN(x, STACK_ALIGN)
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/* APIs need to support non-byte addressable architectures */
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#define OCTET_TO_SIZEOFUNIT(X) (X)
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#define SIZEOFUNIT_TO_OCTET(X) (X)
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/* macros convert value of it's argument to a string */
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#define DO_TOSTR(s) #s
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#define TOSTR(s) DO_TOSTR(s)
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/* concatenate the values of the arguments into one */
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#define DO_CONCAT(x, y) x ## y
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#define CONCAT(x, y) DO_CONCAT(x, y)
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/*
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* SOC-specific function to get the IRQ number generating the interrupt.
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* __soc_get_irq returns a bitfield of pending IRQs.
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*/
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extern uint32_t __soc_get_irq(void);
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void _arch_irq_enable(unsigned int irq);
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void _arch_irq_disable(unsigned int irq);
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int _arch_irq_is_enabled(unsigned int irq);
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/**
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* Configure a static interrupt.
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*
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* All arguments must be computable by the compiler at build time.
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*
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* Internally this function does a few things:
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*
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* 1. The enum statement has no effect but forces the compiler to only
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* accept constant values for the irq_p parameter, very important as the
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* numerical IRQ line is used to create a named section.
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*
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* 2. An instance of _IsrTableEntry is created containing the ISR and its
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* parameter. If you look at how _sw_isr_table is created, each entry in the
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* array is in its own section named by the IRQ line number. What we are doing
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* here is to override one of the default entries (which points to the
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* spurious IRQ handler) with what was supplied here.
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*
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* 3. interrupt priority is not supported by pulpino core
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*
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* @param irq_p IRQ line number
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* @param priority_p Interrupt priority
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* @param isr_p Interrupt service routine
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* @param isr_param_p ISR parameter
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* @param flags_p IRQ options
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*
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* @return The vector assigned to this interrupt
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*/
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#define _ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
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({ \
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enum { IRQ = irq_p }; \
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static struct _IsrTableEntry _CONCAT(_isr_irq, irq_p) \
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__attribute__ ((used)) \
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__attribute__ ((section(STRINGIFY(_CONCAT(.gnu.linkonce.isr_irq, irq_p))))) = \
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{isr_param_p, isr_p}; \
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irq_p; \
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})
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/*
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* use atomic instruction csrrc to lock global irq
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* csrrc: atomic read and clear bits in CSR register
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*/
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static ALWAYS_INLINE unsigned int _arch_irq_lock(void)
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{
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unsigned int key, mstatus;
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__asm__ volatile ("csrrc %0, mstatus, %1"
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: "=r" (mstatus)
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: "r" (SOC_MSTATUS_IEN)
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: "memory");
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key = (mstatus & SOC_MSTATUS_IEN);
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return key;
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}
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/*
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* use atomic instruction csrrs to unlock global irq
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* csrrs: atomic read and set bits in CSR register
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*/
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static ALWAYS_INLINE void _arch_irq_unlock(unsigned int key)
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{
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unsigned int mstatus;
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__asm__ volatile ("csrrs %0, mstatus, %1"
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: "=r" (mstatus)
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: "r" (key & SOC_MSTATUS_IEN)
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: "memory");
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}
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#endif /*_ASMLANGUAGE */
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#if defined(CONFIG_SOC_RISCV32_PULPINO)
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#include <arch/riscv32/pulpino/asm_inline.h>
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#elif defined(CONFIG_SOC_RISCV32_QEMU)
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#include <arch/riscv32/riscv32-qemu/asm_inline.h>
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif
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