zephyr/dts/riscv
Sylvio Alves b58394bbbd sensor: esp32c3: fix coretemp DTS register address
Remove 0x prefix to avoid build warning.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2022-12-24 16:58:38 +01:00
..
andes dts: bindings: spi: add andes spi driver 2022-09-07 15:34:47 +02:00
espressif sensor: esp32c3: fix coretemp DTS register address 2022-12-24 16:58:38 +01:00
gigadevice dts: bindings: gd32-dma-base: add `gd,mem2mem` property 2022-12-22 13:43:49 +01:00
ite ITE: soc: it81xx2: Add new variant of it81xx2cx related configuration 2022-12-02 11:29:00 +01:00
microsemi dts: riscv: microsemi-miv: define CLINT 2022-08-02 09:12:31 +02:00
openisa dts: riscv: Remove label property from devicetrees 2022-07-26 12:57:23 -05:00
sifive dts: riscv: sifive: use sifive,clint0 2022-08-02 09:12:31 +02:00
starfive dts: riscv: starfive: align clint description with Linux 2022-08-02 09:12:31 +02:00
telink dts: riscv: telink: add DT entry for machine timer 2022-08-02 09:12:31 +02:00
mpfs-icicle.dtsi include: add missing zephyr/ prefixes 2022-08-02 18:03:58 +01:00
neorv32.dtsi dts: riscv: neorv32: define machine timer 2022-08-02 09:12:31 +02:00
riscv32-litex-vexriscv.dtsi dts: riscv: Remove label property from devicetrees 2022-07-26 12:57:23 -05:00
virt.dtsi dts: riscv: virt: use sifive,clint0 2022-08-02 09:12:31 +02:00