209 lines
4.9 KiB
C
209 lines
4.9 KiB
C
/*
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* Copyright (c) 2015 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file Driver for DesignWare PWM driver.
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*
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* The timer IP block can act as both timer and PWM. Under PWM mode, each port
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* has two registers to specify how long to stay low, and how long to stay high.
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* Care must be taken so that PWM and timer functions are not both enabled
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* on one port.
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*
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* The set of registers for each timer repeats every 0x14.
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* However, the load count 2 starts at 0xB0, and repeats every 0x04.
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* Accessing load count 2 registers, thus, requires some special treatment.
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*/
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#include <errno.h>
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#include <kernel.h>
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#include <drivers/pwm.h>
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/* Register for component version */
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#define REG_COMP_VER 0xAC
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/* Timer Load Count register, for pin to stay low. */
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#define REG_TMR_LOAD_CNT 0x00
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/* Control for timer */
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#define REG_TMR_CTRL 0x08
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/* Offset from Timer 1 Load Count address
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* for other timers. (e.g. Timer 2 address +0x14,
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* timer 3 address + 0x28, etc.)
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*
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* This also applies to other registers for
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* different timers (except load count 2).
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*/
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#define REG_OFFSET 0x14
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/* Timer Load Count 2 register, for pin to stay high. */
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#define REG_TMR_LOAD_CNT2 0xB0
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/* Offset from Timer 1 Load Count 2 address
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* for other timers. (e.g. Timer 2 address +0x04,
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* timer 3 address + 0x08, etc.)
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*/
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#define REG_OFFSET_LOAD_CNT2 0x04
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/* Default for control register:
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* PWM mode, interrupt masked, user-defined count mode, but disabled
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*/
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#define TIMER_INIT_CTRL 0x0E
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struct pwm_dw_config {
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/** Base address of registers */
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uint32_t addr;
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/** Number of ports */
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uint32_t num_ports;
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};
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/**
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* Find the base address for each timer
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*
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* @param dev Device struct
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* @param timer Which timer
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*
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* @return The base address of that particular timer
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*/
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static inline int pwm_dw_timer_base_addr(const struct device *dev,
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uint32_t timer)
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{
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const struct pwm_dw_config * const cfg =
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(const struct pwm_dw_config *)dev->config;
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return (cfg->addr + (timer * REG_OFFSET));
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}
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/**
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* Find the load count 2 address for each timer
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*
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* @param dev Device struct
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* @param timer Which timer
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*
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* @return The load count 2 address of that particular timer
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*/
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static inline int pwm_dw_timer_ldcnt2_addr(const struct device *dev,
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uint32_t timer)
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{
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const struct pwm_dw_config * const cfg =
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(const struct pwm_dw_config *)dev->config;
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return (cfg->addr + REG_TMR_LOAD_CNT2 + (timer * REG_OFFSET_LOAD_CNT2));
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}
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static int __set_one_port(const struct device *dev, uint32_t pwm,
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uint32_t on, uint32_t off)
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{
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uint32_t reg_addr;
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reg_addr = pwm_dw_timer_base_addr(dev, pwm);
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/* Disable timer to prevent any output */
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sys_write32(TIMER_INIT_CTRL, (reg_addr + REG_TMR_CTRL));
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if ((off == 0U) || (on == 0U)) {
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/* stop PWM if so specified */
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return 0;
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}
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/* write timer for pin to stay low */
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sys_write32(off, (reg_addr + REG_TMR_LOAD_CNT));
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/* write timer for pin to stay high */
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sys_write32(on, pwm_dw_timer_ldcnt2_addr(dev, pwm));
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/* Enable timer so it starts running and counting */
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sys_write32((TIMER_INIT_CTRL | 0x01), (reg_addr + REG_TMR_CTRL));
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return 0;
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}
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/**
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* Set the period and the pulse of PWM.
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*
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*
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* Assumes a nominal system clock of 32MHz, each count of on/off represents
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* 31.25ns (e.g. on == 2 means the pin stays high for 62.5ns).
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* The duration of 1 count depends on system clock. Refer to the hardware
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* manual for more information.
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*
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* @param dev Device struct
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* @param pwm Which PWM pin to set
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* @param period_cycles Period in clock cycles of the pwm.
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* @param pulse_cycles PWM width in clock cycles
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* @param flags Flags for pin configuration (polarity).
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*
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* @return 0
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*/
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static int pwm_dw_pin_set_cycles(const struct device *dev,
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uint32_t pwm, uint32_t period_cycles,
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uint32_t pulse_cycles, pwm_flags_t flags)
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{
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const struct pwm_dw_config * const cfg =
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(const struct pwm_dw_config *)dev->config;
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int i;
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uint32_t on, off;
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/* make sure the PWM port exists */
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if (pwm >= cfg->num_ports) {
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return -EIO;
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}
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if (flags) {
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/* PWM polarity not supported (yet?) */
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return -ENOTSUP;
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}
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if (period_cycles == 0U || pulse_cycles > period_cycles) {
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return -EINVAL;
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}
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on = pulse_cycles;
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off = period_cycles - pulse_cycles;
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if (off == 0U) {
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on--;
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off++;
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}
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return __set_one_port(dev, pwm, on, off);
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}
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static struct pwm_driver_api pwm_dw_drv_api_funcs = {
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.pin_set = pwm_dw_pin_set_cycles,
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};
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/**
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* @brief Initialization function of PCA9685
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*
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* @param dev Device struct
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* @return 0 if successful, failed otherwise.
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*/
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int pwm_dw_init(const struct device *dev)
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{
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return 0;
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}
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/* Initialization for PWM_DW */
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#if defined(CONFIG_PWM_DW)
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#include <device.h>
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#include <init.h>
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static struct pwm_dw_config pwm_dw_cfg = {
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.addr = PWM_DW_BASE_ADDR,
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.num_ports = PWM_DW_NUM_PORTS,
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};
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DEVICE_AND_API_INIT(pwm_dw_0, CONFIG_PWM_DW_0_DRV_NAME, pwm_dw_init,
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NULL, &pwm_dw_cfg,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&pwm_dw_drv_api_funcs);
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#endif /* CONFIG_PWM_DW */
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