263 lines
6.1 KiB
C
263 lines
6.1 KiB
C
/*
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* Copyright (c) 2019 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT microchip_xec_ps2
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#include <errno.h>
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#include <device.h>
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#include <drivers/ps2.h>
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#include <soc.h>
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#include <logging/log.h>
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#define LOG_LEVEL CONFIG_PS2_LOG_LEVEL
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LOG_MODULE_REGISTER(ps2_mchp_xec);
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/* in 50us units */
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#define PS2_TIMEOUT 10000
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struct ps2_xec_config {
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PS2_Type *base;
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uint8_t girq_id;
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uint8_t girq_bit;
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uint8_t isr_nvic;
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};
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struct ps2_xec_data {
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ps2_callback_t callback_isr;
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struct k_sem tx_lock;
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};
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static int ps2_xec_configure(const struct device *dev,
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ps2_callback_t callback_isr)
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{
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const struct ps2_xec_config *config = dev->config;
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struct ps2_xec_data *data = dev->data;
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PS2_Type *base = config->base;
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uint8_t __attribute__((unused)) dummy;
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if (!callback_isr) {
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return -EINVAL;
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}
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data->callback_isr = callback_isr;
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/* In case the self test for a PS2 device already finished and
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* set the SOURCE bit to 1 we clear it before enabling the
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* interrupts. Instances must be allocated before the BAT or
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* the host may time out.
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*/
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MCHP_GIRQ_SRC(config->girq_id) = BIT(config->girq_bit);
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dummy = base->TRX_BUFF;
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base->STATUS = MCHP_PS2_STATUS_RW1C_MASK;
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/* Enable FSM and init instance in rx mode*/
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base->CTRL = MCHP_PS2_CTRL_EN_POS;
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/* We enable the interrupts in the EC aggregator so that the
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* result can be forwarded to the ARM NVIC
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*/
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MCHP_GIRQ_ENSET(config->girq_id) = BIT(config->girq_bit);
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k_sem_give(&data->tx_lock);
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return 0;
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}
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static int ps2_xec_write(const struct device *dev, uint8_t value)
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{
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const struct ps2_xec_config *config = dev->config;
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struct ps2_xec_data *data = dev->data;
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PS2_Type *base = config->base;
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int i = 0;
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uint8_t __attribute__((unused)) dummy;
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if (k_sem_take(&data->tx_lock, K_NO_WAIT)) {
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return -EACCES;
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}
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/* Allow the PS2 controller to complete a RX transaction. This
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* is because the channel may be actively receiving data.
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* In addition, it is necessary to wait for a previous TX
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* transaction to complete. The PS2 block has a single
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* FSM.
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*/
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while (((base->STATUS &
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(MCHP_PS2_STATUS_RX_BUSY | MCHP_PS2_STATUS_TX_IDLE))
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!= MCHP_PS2_STATUS_TX_IDLE) && (i < PS2_TIMEOUT)) {
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k_busy_wait(50);
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i++;
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}
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if (unlikely(i == PS2_TIMEOUT)) {
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LOG_DBG("PS2 write timed out");
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return -ETIMEDOUT;
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}
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/* Inhibit ps2 controller and clear status register */
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base->CTRL = 0x00;
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/* Read to clear data ready bit in the status register*/
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dummy = base->TRX_BUFF;
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k_sleep(K_MSEC(1));
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base->STATUS = MCHP_PS2_STATUS_RW1C_MASK;
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/* Switch the interface to TX mode and enable state machine */
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base->CTRL = MCHP_PS2_CTRL_TR_TX | MCHP_PS2_CTRL_EN;
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/* Write value to TX/RX register */
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base->TRX_BUFF = value;
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k_sem_give(&data->tx_lock);
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return 0;
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}
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static int ps2_xec_inhibit_interface(const struct device *dev)
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{
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const struct ps2_xec_config *config = dev->config;
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struct ps2_xec_data *data = dev->data;
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PS2_Type *base = config->base;
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if (k_sem_take(&data->tx_lock, K_MSEC(10)) != 0) {
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return -EACCES;
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}
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base->CTRL = 0x00;
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MCHP_GIRQ_SRC(config->girq_id) = BIT(config->girq_bit);
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NVIC_ClearPendingIRQ(config->isr_nvic);
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k_sem_give(&data->tx_lock);
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return 0;
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}
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static int ps2_xec_enable_interface(const struct device *dev)
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{
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const struct ps2_xec_config *config = dev->config;
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struct ps2_xec_data *data = dev->data;
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PS2_Type *base = config->base;
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MCHP_GIRQ_SRC(config->girq_id) = BIT(config->girq_bit);
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base->CTRL = MCHP_PS2_CTRL_EN;
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k_sem_give(&data->tx_lock);
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return 0;
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}
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static void ps2_xec_isr(const struct device *dev)
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{
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const struct ps2_xec_config *config = dev->config;
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struct ps2_xec_data *data = dev->data;
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PS2_Type *base = config->base;
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uint32_t status;
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MCHP_GIRQ_SRC(config->girq_id) = BIT(config->girq_bit);
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/* Read and clear status */
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status = base->STATUS;
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if (status & MCHP_PS2_STATUS_RXD_RDY) {
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base->CTRL = 0x00;
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if (data->callback_isr) {
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data->callback_isr(dev, base->TRX_BUFF);
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}
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} else if (status &
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(MCHP_PS2_STATUS_TX_TMOUT | MCHP_PS2_STATUS_TX_ST_TMOUT)) {
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/* Clear sticky bits and go to read mode */
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base->STATUS = MCHP_PS2_STATUS_RW1C_MASK;
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LOG_ERR("TX time out: %0x", status);
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}
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/* The control register reverts to RX automatically after
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* transmiting the data
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*/
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base->CTRL = MCHP_PS2_CTRL_EN;
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}
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static const struct ps2_driver_api ps2_xec_driver_api = {
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.config = ps2_xec_configure,
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.read = NULL,
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.write = ps2_xec_write,
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.disable_callback = ps2_xec_inhibit_interface,
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.enable_callback = ps2_xec_enable_interface,
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};
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#ifdef CONFIG_PS2_XEC_0
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static int ps2_xec_init_0(const struct device *dev);
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static const struct ps2_xec_config ps2_xec_config_0 = {
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.base = (PS2_Type *) DT_INST_REG_ADDR(0),
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.girq_id = DT_INST_PROP(0, girq),
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.girq_bit = DT_INST_PROP(0, girq_bit),
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.isr_nvic = DT_INST_IRQN(0),
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};
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static struct ps2_xec_data ps2_xec_port_data_0;
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DEVICE_AND_API_INIT(ps2_xec_0, DT_INST_LABEL(0),
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&ps2_xec_init_0,
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&ps2_xec_port_data_0, &ps2_xec_config_0,
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POST_KERNEL, CONFIG_PS2_INIT_PRIORITY,
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&ps2_xec_driver_api);
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static int ps2_xec_init_0(const struct device *dev)
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{
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ARG_UNUSED(dev);
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struct ps2_xec_data *data = dev->data;
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k_sem_init(&data->tx_lock, 0, 1);
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IRQ_CONNECT(DT_INST_IRQN(0),
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DT_INST_IRQ(0, priority),
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ps2_xec_isr, DEVICE_GET(ps2_xec_0), 0);
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irq_enable(DT_INST_IRQN(0));
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return 0;
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}
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#endif /* CONFIG_PS2_XEC_0 */
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#ifdef CONFIG_PS2_XEC_1
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static int ps2_xec_init_1(const struct device *dev);
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static const struct ps2_xec_config ps2_xec_config_1 = {
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.base = (PS2_Type *) DT_INST_REG_ADDR(1),
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.girq_id = DT_INST_PROP(1, girq),
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.girq_bit = DT_INST_PROP(1, girq_bit),
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.isr_nvic = DT_INST_IRQN(1),
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};
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static struct ps2_xec_data ps2_xec_port_data_1;
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DEVICE_AND_API_INIT(ps2_xec_1, DT_INST_LABEL(1),
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&ps2_xec_init_1,
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&ps2_xec_port_data_1, &ps2_xec_config_1,
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POST_KERNEL, CONFIG_PS2_INIT_PRIORITY,
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&ps2_xec_driver_api);
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static int ps2_xec_init_1(const struct device *dev)
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{
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ARG_UNUSED(dev);
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struct ps2_xec_data *data = dev->data;
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k_sem_init(&data->tx_lock, 0, 1);
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IRQ_CONNECT(DT_INST_IRQN(1),
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DT_INST_IRQ(1, priority),
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ps2_xec_isr, DEVICE_GET(ps2_xec_1), 0);
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irq_enable(DT_INST_IRQN(1));
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return 0;
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}
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#endif /* CONFIG_PS2_XEC_1 */
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