168 lines
3.8 KiB
C
168 lines
3.8 KiB
C
/* irq-test-common.h - IRQ utilities for tests */
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/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/*
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DESCRIPTION
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Interrupt stuff, abstracted across CPU architectures.
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*/
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#ifndef _IRQ_TEST_COMMON__H_
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#define _IRQ_TEST_COMMON__H_
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#if defined(CONFIG_X86)
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#define IRQ_PRIORITY 3
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#elif defined(CONFIG_ARM)
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#if defined(CONFIG_CPU_CORTEX_M)
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#define IRQ_PRIORITY _EXC_PRIO(3)
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#endif /* CONFIG_CPU_CORTEX_M */
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#endif
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/*
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* NUM_SW_IRQS must be defined before this file is included, and it
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* currently only supports 1 or 2 as valid values.
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*/
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#if !defined(NUM_SW_IRQS)
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#error NUM_SW_IRQS must be defined before including irq-test-common.h
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#elif NUM_SW_IRQS < 1 || NUM_SW_IRQS > 2
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#error NUM_SW_IRQS only supports 1 or 2 IRQs
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#endif
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#if defined(CONFIG_X86)
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static NANO_CPU_INT_STUB_DECL(nanoIntStub1);
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#if NUM_SW_IRQS >= 2
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static NANO_CPU_INT_STUB_DECL(nanoIntStub2);
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#endif /* NUM_SW_IRQS >= 2 */
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#endif
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/** Declares a void-void function pointer to test the ISR. */
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typedef void (*vvfn)(void);
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/** Declares a void-void_pointer function pointer to test the ISR. */
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typedef void (*vvpfn)(void *);
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#if defined(CONFIG_X86)
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/*
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* Opcode for generating a software interrupt. The ISR associated with each
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* of these software interrupts will call either nano_isr_lifo_put() or
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* nano_isr_lifo_get(). The imm8 data in the opcode sequence will need to be
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* filled in after calling IRQ_CONNECT().
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*/
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static char sw_isr_trigger_0[] =
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{
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0xcd, /* OPCODE: INT imm8 */
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0x00, /* imm8 data (vector to trigger) filled in at runtime */
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0xc3 /* OPCODE: RET (near) */
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};
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#if NUM_SW_IRQS >= 2
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static char sw_isr_trigger_1[] =
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{
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/* same as above */
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0xcd,
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0x00,
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0xc3
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};
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#endif /* NUM_SW_IRQS >= 2 */
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#elif defined(CONFIG_ARM)
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#if defined(CONFIG_CPU_CORTEX_M)
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#include <nanokernel.h>
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static inline void sw_isr_trigger_0(void)
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{
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_NvicSwInterruptTrigger(0);
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}
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#if NUM_SW_IRQS >= 2
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static inline void sw_isr_trigger_1(void)
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{
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_NvicSwInterruptTrigger(1);
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}
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#endif /* NUM_SW_IRQS >= 2 */
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#endif /* CONFIG_CPU_CORTEX_M */
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#endif
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/** Defines the ISR initialization information. */
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struct isrInitInfo
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{
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/** Declares the void-void function pointer for the ISR. */
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vvpfn isr[2];
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/** Declares a space for the information. */
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void *arg[2];
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};
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/*******************************************************************************
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*
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* initIRQ - init interrupts
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*
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*/
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static int initIRQ
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(
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struct isrInitInfo *i
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)
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{
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#if defined(CONFIG_X86)
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int vector; /* vector to which interrupt is connected */
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if (i->isr[0])
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{
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vector = IRQ_CONNECT(NANO_SOFT_IRQ, IRQ_PRIORITY, i->isr[0],
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i->arg[0], nanoIntStub1, 0);
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if (-1 == vector)
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{
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return -1;
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}
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sw_isr_trigger_0[1] = vector;
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}
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#if NUM_SW_IRQS >= 2
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if (i->isr[1])
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{
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vector = IRQ_CONNECT(NANO_SOFT_IRQ, IRQ_PRIORITY, i->isr[1],
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i->arg[1], nanoIntStub2, 0);
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if (-1 == vector)
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{
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return -1;
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}
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sw_isr_trigger_1[1] = vector;
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}
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#endif /* NUM_SW_IRQS >= 2 */
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#elif defined(CONFIG_ARM)
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#if defined(CONFIG_CPU_CORTEX_M)
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if (i->isr[0])
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{
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(void) IRQ_CONNECT(0, IRQ_PRIORITY, i->isr[0], i->arg[0], 0);
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irq_enable (0);
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}
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if (i->isr[1])
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{
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(void) IRQ_CONNECT(1, IRQ_PRIORITY, i->isr[1], i->arg[1], 0);
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irq_enable (1);
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}
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#endif /* CONFIG_CPU_CORTEX_M */
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#endif /* CONFIG_X86 */
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return 0;
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}
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#endif /* _IRQ_TEST_COMMON__H_ */
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