55 lines
1.8 KiB
C
55 lines
1.8 KiB
C
/*
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* Copyright (c) 2018 Linaro, Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/kernel.h>
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#include <kernel_internal.h>
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extern const int _k_neg_eagain;
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/* The 'key' actually represents the BASEPRI register
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* prior to disabling interrupts via the BASEPRI mechanism.
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*
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* arch_swap() itself does not do much.
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*
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* It simply stores the intlock key (the BASEPRI value) parameter into
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* current->basepri, and then triggers a PendSV exception, which does
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* the heavy lifting of context switching.
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* This is the only place we have to save BASEPRI since the other paths to
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* z_arm_pendsv all come from handling an interrupt, which means we know the
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* interrupts were not locked: in that case the BASEPRI value is 0.
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*
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* Given that arch_swap() is called to effect a cooperative context switch,
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* only the caller-saved integer registers need to be saved in the thread of the
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* outgoing thread. This is all performed by the hardware, which stores it in
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* its exception stack frame, created when handling the z_arm_pendsv exception.
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*
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* On ARMv6-M, the intlock key is represented by the PRIMASK register,
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* as BASEPRI is not available.
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*/
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int arch_swap(unsigned int key)
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{
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/* store off key and return value */
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_current->arch.basepri = key;
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_current->arch.swap_return_value = _k_neg_eagain;
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#if defined(CONFIG_CPU_CORTEX_M)
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/* set pending bit to make sure we will take a PendSV exception */
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SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
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/* clear mask or enable all irqs to take a pendsv */
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irq_unlock(0);
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#elif defined(CONFIG_CPU_AARCH32_CORTEX_R) || defined(CONFIG_CPU_AARCH32_CORTEX_A)
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z_arm_cortex_r_svc();
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irq_unlock(key);
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#endif
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/* Context switch is performed here. Returning implies the
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* thread has been context-switched-in again.
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*/
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return _current->arch.swap_return_value;
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}
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