387 lines
8.5 KiB
C
387 lines
8.5 KiB
C
/*
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* Copyright (c) 2016 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file Driver for the Atmel SAM3 PIO Controller.
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*/
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#include <errno.h>
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#include <kernel.h>
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#include <device.h>
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#include <init.h>
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#include <soc.h>
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#include <gpio.h>
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#include "gpio_utils.h"
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typedef void (*config_func_t)(struct device *dev);
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/* Configuration data */
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struct gpio_sam3_config {
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Pio *port;
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config_func_t config_func;
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};
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struct gpio_sam3_runtime {
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/* callbacks */
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sys_slist_t cb;
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};
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static void _config(struct device *dev, u32_t mask, int flags)
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{
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const struct gpio_sam3_config *cfg = dev->config->config_info;
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/* Setup the pin direction */
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if ((flags & GPIO_DIR_MASK) == GPIO_DIR_OUT) {
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cfg->port->PIO_OER = mask;
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} else {
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cfg->port->PIO_ODR = mask;
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}
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/* Setup interrupt config */
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if (flags & GPIO_INT) {
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if (flags & GPIO_INT_DOUBLE_EDGE) {
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cfg->port->PIO_AIMDR = mask;
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} else {
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cfg->port->PIO_AIMER = mask;
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if (flags & GPIO_INT_EDGE) {
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cfg->port->PIO_ESR = mask;
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} else {
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cfg->port->PIO_LSR = mask;
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}
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if (flags & GPIO_INT_ACTIVE_HIGH) {
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/* Trigger in high level or rising edge */
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cfg->port->PIO_REHLSR = mask;
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} else {
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/* Trigger in low level or falling edge */
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cfg->port->PIO_FELLSR = mask;
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}
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}
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}
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/* Pull-up? */
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if ((flags & GPIO_PUD_MASK) == GPIO_PUD_PULL_UP) {
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/* Enable pull-up */
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cfg->port->PIO_PUER = mask;
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} else {
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/* Disable pull-up */
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cfg->port->PIO_PUDR = mask;
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}
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/* Debounce */
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if (flags & GPIO_INT_DEBOUNCE) {
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cfg->port->PIO_DIFSR = mask;
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} else {
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cfg->port->PIO_SCIFSR = mask;
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}
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cfg->port->PIO_PER = mask;
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}
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/**
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* @brief Configure pin or port
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*
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* @param dev Device struct
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* @param access_op Access operation (pin or port)
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* @param pin The pin number
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* @param flags Flags of pin or port
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*
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* @return 0 if successful, failed otherwise
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*/
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static int gpio_sam3_config(struct device *dev, int access_op,
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u32_t pin, int flags)
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{
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switch (access_op) {
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case GPIO_ACCESS_BY_PIN:
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_config(dev, BIT(pin), flags);
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break;
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case GPIO_ACCESS_BY_PORT:
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_config(dev, (0xFFFFFFFF), flags);
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break;
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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/**
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* @brief Set the pin or port output
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*
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* @param dev Device struct
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* @param access_op Access operation (pin or port)
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* @param pin The pin number
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* @param value Value to set (0 or 1)
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*
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* @return 0 if successful, failed otherwise
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*/
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static int gpio_sam3_write(struct device *dev, int access_op,
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u32_t pin, u32_t value)
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{
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const struct gpio_sam3_config *cfg = dev->config->config_info;
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switch (access_op) {
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case GPIO_ACCESS_BY_PIN:
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if (value) {
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/* set the pin */
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cfg->port->PIO_SODR = BIT(pin);
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} else {
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/* clear the pin */
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cfg->port->PIO_CODR = BIT(pin);
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}
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break;
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case GPIO_ACCESS_BY_PORT:
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if (value) {
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/* set all pins */
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cfg->port->PIO_SODR = 0xFFFFFFFF;
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} else {
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/* clear all pins */
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cfg->port->PIO_CODR = 0xFFFFFFFF;
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}
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break;
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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/**
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* @brief Read the pin or port status
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*
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* @param dev Device struct
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* @param access_op Access operation (pin or port)
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* @param pin The pin number
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* @param value Value of input pin(s)
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*
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* @return 0 if successful, failed otherwise
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*/
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static int gpio_sam3_read(struct device *dev, int access_op,
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u32_t pin, u32_t *value)
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{
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const struct gpio_sam3_config *cfg = dev->config->config_info;
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*value = cfg->port->PIO_PDSR;
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switch (access_op) {
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case GPIO_ACCESS_BY_PIN:
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*value = (*value >> pin) & 0x01;
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break;
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case GPIO_ACCESS_BY_PORT:
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break;
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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static void gpio_sam3_isr(void *arg)
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{
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struct device *dev = (struct device *)arg;
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const struct gpio_sam3_config *cfg = dev->config->config_info;
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struct gpio_sam3_runtime *context = dev->driver_data;
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u32_t int_stat;
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int_stat = cfg->port->PIO_ISR;
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_gpio_fire_callbacks(&context->cb, dev, int_stat);
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}
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static int gpio_sam3_manage_callback(struct device *dev,
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struct gpio_callback *callback,
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bool set)
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{
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struct gpio_sam3_runtime *context = dev->driver_data;
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return _gpio_manage_callback(&context->cb, callback, set);
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}
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static int gpio_sam3_enable_callback(struct device *dev,
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int access_op, u32_t pin)
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{
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const struct gpio_sam3_config *cfg = dev->config->config_info;
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u32_t mask;
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switch (access_op) {
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case GPIO_ACCESS_BY_PIN:
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mask = BIT(pin);
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break;
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case GPIO_ACCESS_BY_PORT:
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mask = 0xFFFFFFFF;
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break;
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default:
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return -ENOTSUP;
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}
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cfg->port->PIO_IER |= mask;
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return 0;
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}
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static int gpio_sam3_disable_callback(struct device *dev,
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int access_op, u32_t pin)
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{
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const struct gpio_sam3_config *cfg = dev->config->config_info;
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u32_t mask;
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switch (access_op) {
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case GPIO_ACCESS_BY_PIN:
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mask = BIT(pin);
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break;
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case GPIO_ACCESS_BY_PORT:
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mask = 0xFFFFFFFF;
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break;
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default:
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return -ENOTSUP;
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}
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cfg->port->PIO_IDR |= mask;
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return 0;
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}
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static const struct gpio_driver_api gpio_sam3_drv_api_funcs = {
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.config = gpio_sam3_config,
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.write = gpio_sam3_write,
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.read = gpio_sam3_read,
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.manage_callback = gpio_sam3_manage_callback,
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.enable_callback = gpio_sam3_enable_callback,
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.disable_callback = gpio_sam3_disable_callback,
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};
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/**
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* @brief Initialization function of MMIO
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*
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* @param dev Device struct
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* @return 0 if successful, failed otherwise.
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*/
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static int gpio_sam3_init(struct device *dev)
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{
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const struct gpio_sam3_config *cfg = dev->config->config_info;
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cfg->config_func(dev);
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return 0;
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}
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/* Port A */
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#ifdef CONFIG_GPIO_ATMEL_SAM3_PORTA
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static void gpio_sam3_config_a(struct device *dev);
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static const struct gpio_sam3_config gpio_sam3_a_cfg = {
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.port = PIOA,
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.config_func = gpio_sam3_config_a,
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};
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static struct gpio_sam3_runtime gpio_sam3_a_runtime;
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DEVICE_AND_API_INIT(gpio_sam3_a, CONFIG_GPIO_ATMEL_SAM3_PORTA_DEV_NAME,
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gpio_sam3_init, &gpio_sam3_a_runtime, &gpio_sam3_a_cfg,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&gpio_sam3_drv_api_funcs);
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static void gpio_sam3_config_a(struct device *dev)
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{
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/* Enable clock for PIO controller */
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PMC->PMC_PCER0 = BIT(ID_PIOA);
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IRQ_CONNECT(PIOA_IRQn, CONFIG_GPIO_ATMEL_SAM3_PORTA_IRQ_PRI,
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gpio_sam3_isr, DEVICE_GET(gpio_sam3_a), 0);
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irq_enable(PIOA_IRQn);
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}
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#endif /* CONFIG_GPIO_ATMEL_SAM3_PORTA */
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/* Port B */
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#ifdef CONFIG_GPIO_ATMEL_SAM3_PORTB
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static void gpio_sam3_config_b(struct device *dev);
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static const struct gpio_sam3_config gpio_sam3_b_cfg = {
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.port = PIOB,
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.config_func = gpio_sam3_config_b,
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};
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static struct gpio_sam3_runtime gpio_sam3_b_runtime;
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DEVICE_AND_API_INIT(gpio_sam3_b, CONFIG_GPIO_ATMEL_SAM3_PORTB_DEV_NAME,
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gpio_sam3_init, &gpio_sam3_b_runtime, &gpio_sam3_b_cfg,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&gpio_sam3_drv_api_funcs);
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static void gpio_sam3_config_b(struct device *dev)
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{
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/* Enable clock for PIO controller */
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PMC->PMC_PCER0 = BIT(ID_PIOB);
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IRQ_CONNECT(PIOB_IRQn, CONFIG_GPIO_ATMEL_SAM3_PORTB_IRQ_PRI,
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gpio_sam3_isr, DEVICE_GET(gpio_sam3_b), 0);
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irq_enable(PIOB_IRQn);
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}
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#endif /* CONFIG_GPIO_ATMEL_SAM3_PORTB */
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/* Port C */
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#ifdef CONFIG_GPIO_ATMEL_SAM3_PORTC
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static void gpio_sam3_config_c(struct device *dev);
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static const struct gpio_sam3_config gpio_sam3_c_cfg = {
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.port = PIOC,
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.config_func = gpio_sam3_config_c,
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};
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static struct gpio_sam3_runtime gpio_sam3_c_runtime;
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DEVICE_AND_API_INIT(gpio_sam3_c, CONFIG_GPIO_ATMEL_SAM3_PORTC_DEV_NAME,
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gpio_sam3_init, &gpio_sam3_c_runtime, &gpio_sam3_c_cfg,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&gpio_sam3_drv_api_funcs);
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static void gpio_sam3_config_c(struct device *dev)
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{
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/* Enable clock for PIO controller */
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PMC->PMC_PCER0 = BIT(ID_PIOC);
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IRQ_CONNECT(PIOC_IRQn, CONFIG_GPIO_ATMEL_SAM3_PORTC_IRQ_PRI,
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gpio_sam3_isr, DEVICE_GET(gpio_sam3_c), 0);
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irq_enable(PIOC_IRQn);
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}
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#endif /* CONFIG_GPIO_ATMEL_SAM3_PORTA */
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/* Port D */
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#ifdef CONFIG_GPIO_ATMEL_SAM3_PORTD
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static void gpio_sam3_config_d(struct device *dev);
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static const struct gpio_sam3_config gpio_sam3_d_cfg = {
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.port = PIOD,
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.config_func = gpio_sam3_config_d,
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};
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static struct gpio_sam3_runtime gpio_sam3_d_runtime;
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DEVICE_AND_API_INIT(gpio_sam3_d, CONFIG_GPIO_ATMEL_SAM3_PORTD_DEV_NAME,
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gpio_sam3_init, &gpio_sam3_d_runtime, &gpio_sam3_d_cfg,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&gpio_sam3_drv_api_funcs);
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static void gpio_sam3_config_d(struct device *dev)
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{
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/* Enable clock for PIO controller */
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PMC->PMC_PCER0 = BIT(ID_PIOD);
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IRQ_CONNECT(PIOD_IRQn, CONFIG_GPIO_ATMEL_SAM3_PORTD_IRQ_PRI,
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gpio_sam3_isr, DEVICE_GET(gpio_sam3_d), 0);
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irq_enable(PIOD_IRQn);
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}
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#endif /* CONFIG_GPIO_ATMEL_SAM3_PORTD */
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