139 lines
2.7 KiB
Plaintext
139 lines
2.7 KiB
Plaintext
/*
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* Copyright 2018 Foundries.io Ltd
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <riscv/rv32m1.dtsi>
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/ {
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aliases {
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intmux = &intmux0;
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system-lptmr = &lptmr0;
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};
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cpus {
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/delete-node/ cpu@1;
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};
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};
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&m4_flash {
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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/* This configuration assumes the Arm cores are disabled, as
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* these base addresses contain the Arm core vector tables if
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* they are used.
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*/
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ri5cy_code_partition: partition@0 {
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label = "ri5cy-code";
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reg = <0x00000000 0x000fff00>;
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};
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ri5cy_vector_partition: partition@fff00 {
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label = "ri5cy-vector";
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reg = <0x000fff00 0x100>;
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};
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};
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};
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/*
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* INTMUX channels below are somewhat arbitrary.
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*
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* The system timer (assumed at LPTMR0) is placed on channel 0, and peripherals
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* are in channel 1. This can be overridden with overlays, e.g. to manage IRQ
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* priorities, and it will Just Work, but using fewer channels here allows
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* disabling unused ones in Kconfig, making the binary smaller.
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*
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* Each enabled channel requires 256 bytes in _sw_isr_table, so the savings for
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* disabling channels can add up.
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*/
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&intmux0 {
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interrupt-parent = <&event0>;
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interrupts = <INTMUX_CH0_IRQ>, <INTMUX_CH1_IRQ>, <INTMUX_CH2_IRQ>, <INTMUX_CH3_IRQ>, <INTMUX_CH4_IRQ>, <INTMUX_CH5_IRQ>, <INTMUX_CH6_IRQ>, <INTMUX_CH7_IRQ>;
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status = "okay";
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};
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&lptmr0 {
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interrupt-parent = <&intmux0>;
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interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH0, 7)>;
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};
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&lptmr1 {
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interrupt-parent = <&intmux0>;
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interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH1, 8)>;
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};
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&lptmr2 {
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interrupt-parent = <&intmux0>;
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interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH1, 22)>;
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};
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&gpioa {
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interrupt-parent = <&event0>;
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interrupts = <18>;
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};
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&gpiob {
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interrupt-parent = <&intmux0>;
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interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH1, 15)>;
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};
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&gpioc {
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interrupt-parent = <&intmux0>;
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interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH1, 16)>;
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};
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&gpiod {
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interrupt-parent = <&intmux0>;
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interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH1, 17)>;
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};
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&gpioe {
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interrupt-parent = <&intmux0>;
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interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH1, 27)>;
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};
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&uart0 {
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interrupt-parent = <&event0>;
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interrupts = <17>;
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};
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&uart1 {
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interrupt-parent = <&intmux0>;
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interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH1, 13)>;
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};
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&uart2 {
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interrupt-parent = <&intmux0>;
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interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH1, 14)>;
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};
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&uart3 {
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interrupt-parent = <&intmux0>;
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interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH1, 26)>;
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};
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&i2c0 {
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interrupt-parent = <&event0>;
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interrupts = <15>;
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};
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&i2c1 {
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interrupt-parent = <&event0>;
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interrupts = <16>;
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};
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&i2c2 {
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interrupt-parent = <&intmux0>;
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interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH1, 11)>;
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};
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&i2c3 {
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interrupt-parent = <&intmux0>;
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interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH1, 24)>;
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};
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