276 lines
7.9 KiB
Plaintext
276 lines
7.9 KiB
Plaintext
# Microchip MEC MCU line
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# Copyright (c) 2018, Intel Corporation
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# Copyright (c) 2022, Microchip Technology Inc.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_FAMILY_MICROCHIP_MEC
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menuconfig MCHP_MEC_UNSIGNED_HEADER
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bool "Create an unsigned output binary with MCHP MEC binary header"
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depends on SOC_SERIES_MEC172X
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help
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On Microchip MEC series chip, the ROM code loads firmware image from flash
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to RAM using a TAG to locate a Header which specifies the location and
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size of the firmware image. Enable this to invoke the mec_spi_gen tool
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which generates an SPI image with TAG, Header, and firmware binary. This
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tool does not produce a signed image which can be authenticated by the
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Boot-ROM. Use the full Microchip SPI image generator program for
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authentication and all other Boot-ROM loader features. Refer to the MCHP
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EVB boards for an example.
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if MCHP_MEC_UNSIGNED_HEADER
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config MCHP_MEC_HEADER_CHIP
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string
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default "mec15xx" if SOC_SERIES_MEC15XX
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default "mec172x" if SOC_SERIES_MEC172X
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choice MCHP_MEC_HEADER_SPI_FREQ_MHZ_CHOICE
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prompt "Clock rate to use for SPI flash"
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default MCHP_MEC_HEADER_SPI_FREQ_MHZ_12
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help
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This selects the SPI clock frequency that will be used for loading
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firmware binary from flash to RAM.
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config MCHP_MEC_HEADER_SPI_FREQ_MHZ_12
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bool "SPI flash clock rate of 12 MHz"
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config MCHP_MEC_HEADER_SPI_FREQ_MHZ_16
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bool "SPI flash clock rate of 16 MHz"
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config MCHP_MEC_HEADER_SPI_FREQ_MHZ_24
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bool "SPI flash clock rate of 24 MHz"
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config MCHP_MEC_HEADER_SPI_FREQ_MHZ_48
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bool "SPI flash clock rate of 48 MHz"
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endchoice
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config MCHP_MEC_HEADER_SPI_FREQ_MHZ
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int
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default 12 if MCHP_MEC_HEADER_SPI_FREQ_MHZ_12
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default 25 if MCHP_MEC_HEADER_SPI_FREQ_MHZ_16
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default 24 if MCHP_MEC_HEADER_SPI_FREQ_MHZ_24
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default 48 if MCHP_MEC_HEADER_SPI_FREQ_MHZ_48
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choice MCHP_MEC_HEADER_SPI_READ_MODE_CHOICE
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prompt "Reading mode used by the SPI flash"
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default MCHP_MEC_HEADER_SPI_READ_MODE_FAST
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help
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This sets the reading mode that can be used by the SPI flash.
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Reading modes supported are normal, fast, dual, and quad.
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config MCHP_MEC_HEADER_SPI_READ_MODE_NORMAL
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bool "SPI flash operates full-duplex with frequency (< 25 MHz)"
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config MCHP_MEC_HEADER_SPI_READ_MODE_FAST
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bool "SPI flash operates full-duplex with fast reading mode"
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config MCHP_MEC_HEADER_SPI_READ_MODE_DUAL
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bool "SPI flash operates with dual data reading mode"
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config MCHP_MEC_HEADER_SPI_READ_MODE_QUAD
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bool "SPI flash operates with quad data reading mode"
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endchoice
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config MCHP_MEC_HEADER_SPI_READ_MODE
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string
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default "slow" if MCHP_MEC_HEADER_SPI_READ_MODE_NORMAL
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default "fast" if MCHP_MEC_HEADER_SPI_READ_MODE_FAST
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default "dual" if MCHP_MEC_HEADER_SPI_READ_MODE_DUAL
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default "quad" if MCHP_MEC_HEADER_SPI_READ_MODE_QUAD
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choice MCHP_MEC_HEADER_FLASH_SIZE_CHOICE
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prompt "Flash size"
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default MCHP_MEC_HEADER_FLASH_SIZE_16M
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help
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This sets the SPI flash size.
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config MCHP_MEC_HEADER_FLASH_SIZE_256K
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bool "SPI flash size 256K Bytes"
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help
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The SPI flash size is 256K Bytes.
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config MCHP_MEC_HEADER_FLASH_SIZE_512K
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bool "SPI flash size 512K Bytes"
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help
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The SPI flash size is 512K Bytes.
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config MCHP_MEC_HEADER_FLASH_SIZE_1M
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bool "SPI flash size 1M Bytes"
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help
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The SPI flash size is 1M Bytes.
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config MCHP_MEC_HEADER_FLASH_SIZE_2M
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bool "SPI flash size 2M Bytes"
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help
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The SPI flash size is 2M Bytes.
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config MCHP_MEC_HEADER_FLASH_SIZE_4M
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bool "SPI flash size 4M Bytes"
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help
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The SPI flash size is 4M Bytes.
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config MCHP_MEC_HEADER_FLASH_SIZE_8M
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bool "SPI flash size 8M Bytes"
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help
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The SPI flash size is 8M Bytes.
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config MCHP_MEC_HEADER_FLASH_SIZE_16M
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bool "SPI flash size 16M Bytes"
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help
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The SPI flash size is 16M Bytes.
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endchoice
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config MCHP_MEC_HEADER_FLASH_SIZE
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int
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default 256 if MCHP_MEC_HEADER_FLASH_SIZE_256K
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default 512 if MCHP_MEC_HEADER_FLASH_SIZE_512K
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default 1024 if MCHP_MEC_HEADER_FLASH_SIZE_1M
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default 2048 if MCHP_MEC_HEADER_FLASH_SIZE_2M
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default 4096 if MCHP_MEC_HEADER_FLASH_SIZE_4M
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default 8192 if MCHP_MEC_HEADER_FLASH_SIZE_8M
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default 16384 if MCHP_MEC_HEADER_FLASH_SIZE_16M
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choice MCHP_MEC_HEADER_SPI_DRVSTR_CHOICE
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prompt "Flash drive strength"
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default MCHP_MEC_HEADER_SPI_DRVSTR_1X
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help
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This sets the SPI flash size.
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config MCHP_MEC_HEADER_SPI_DRVSTR_1X
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bool "SPI flash drive strength multiplier 1"
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help
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The SPI flash size is 256K Bytes.
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config MCHP_MEC_HEADER_SPI_DRVSTR_2X
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bool "SPI flash drive strength multiplier 2"
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help
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The SPI flash size is 256K Bytes.
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config MCHP_MEC_HEADER_SPI_DRVSTR_4X
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bool "SPI flash drive strength multiplier 4"
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help
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The SPI flash size is 512K Bytes.
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config MCHP_MEC_HEADER_SPI_DRVSTR_6X
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bool "SPI flash drive strength multiplier 6"
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help
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The SPI flash size is 1M Bytes.
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endchoice
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config MCHP_MEC_HEADER_SPI_DRVSTR
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string
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default "1x" if MCHP_MEC_HEADER_SPI_DRVSTR_1X
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default "2x" if MCHP_MEC_HEADER_SPI_DRVSTR_2X
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default "4x" if MCHP_MEC_HEADER_SPI_DRVSTR_4X
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default "6x" if MCHP_MEC_HEADER_SPI_DRVSTR_6X
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choice MCHP_MEC_HEADER_SPI_SLEW_RATE_CHOICE
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prompt "Slew rate of SPI pins"
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default MCHP_MEC_HEADER_SPI_SLEW_RATE_SLOW
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help
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This sets the slew rate of the SPI pins. Default is slow
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slew rate which is 1/2 the AHB clock rate. Fast slew is the
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AHB clock rate.
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config MCHP_MEC_HEADER_SPI_SLEW_RATE_SLOW
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bool "SPI pins slew rate is 1/2 AHB frequency"
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config MCHP_MEC_HEADER_SPI_SLEW_RATE_FAST
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bool "SPI pins slew rate is 1x AHB frequency"
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endchoice
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config MCHP_MEC_HEADER_SPI_SLEW_RATE
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string
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default "slow" if MCHP_MEC_HEADER_SPI_SLEW_RATE_SLOW
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default "fast" if MCHP_MEC_HEADER_SPI_SLEW_RATE_FAST
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config MCHP_MEC_HEADER_FLASH_SPI_MODE
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int "Flash SPI Mode"
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range 0 7
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default 0
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help
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This three bit value corresponds to the QMSPI controllers clock idle and
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input/output data phases. Bits[0:2] are CPOL:CPHA_MOSI:CPHA_MISO. Refer
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to the data sheet. Default value is 0 corresponding to SPI Mode 0
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signalling.
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Setting this field to 0 selects mode 0, CPOL=0, CPHA_MOSI=0, CPHA_MISO=0
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Setting this filed to 7 selects mode 3, CPOL=1, CPHA_MOSI=1, CPHA_MISO=1
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config MCHP_HEADER_VERBOSE_OUTPUT
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bool "Debug console output"
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default n
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help
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Enable print output from SPI generator script for debug
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endif # MCHP_MEC_UNSIGNED_HEADER
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# Common debug configuration
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choice
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prompt "MEC debug interface general configuration"
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default SOC_MEC_DEBUG_AND_TRACING
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depends on SOC_SERIES_MEC174X || SOC_SERIES_MEC175X || SOC_SERIES_MECH172X
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help
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Select Debug SoC interface support for MEC SoC family
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config SOC_MEC_DEBUG_DISABLED
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bool "Disable debug support"
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help
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Debug port is disabled, JTAG/SWD cannot be enabled. JTAG_RST#
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pin is ignored. All other JTAG pins can be used as GPIOs
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or other non-JTAG alternate functions.
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config SOC_MEC_DEBUG_WITHOUT_TRACING
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bool "Debug support via Serial wire debug"
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help
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JTAG port in SWD mode.
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config SOC_MEC_DEBUG_AND_TRACING
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bool "Debug support via Serial wire debug with tracing enabled"
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help
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JTAG port is enabled in SWD mode.
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endchoice
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choice
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prompt "MEC debug interface trace configuration"
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default SOC_MEC_DEBUG_AND_SWV_TRACING
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depends on SOC_MEC_DEBUG_AND_TRACING
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help
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Select tracing mode for debug interface
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config SOC_MEC_DEBUG_AND_ETM_TRACING
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bool "Debug support via Serial wire debug"
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help
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JTAG port in SWD mode and ETM as tracing method.
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ETM re-assigns 5 pins for clock and 4-bit data bus.
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Check data sheet for functions shared with ETM.
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config SOC_MEC_DEBUG_AND_SWV_TRACING
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bool "debug support via Serial Wire Debug and Viewer"
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help
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JTAG port in SWD mode and SWV as tracing method.
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Check data sheet for functions shared with SWD and SWV pins.
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endchoice
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# common processor clock divider configuration
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config SOC_MEC_PROC_CLK_DIV
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int "PROC_CLK_DIV"
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default 1
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range 1 48
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help
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This divisor defines a ratio between processor clock (HCLK)
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and main 96 MHz clock (MCK):
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HCLK = MCK / PROC_CLK_DIV
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Allowed divider values: 1, 3, 4, 16, and 48.
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# Select SoC Part No. and configuration options
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rsource "*/Kconfig"
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endif # SOC_FAMILY_MICROCHIP_MEC
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