57 lines
1.2 KiB
YAML
57 lines
1.2 KiB
YAML
# Copyright (c) 2022 BrainCo Inc.
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# SPDX-License-Identifier: Apache-2.0
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description: GigaDevice GD32 ADC
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# gd32 adc irq have some special cases as below:
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# 1. adc number no larger than 3.
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# 2. adc0 and adc1 share the same irq number.
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# 3. For gd32f4xx, adc2 share the same irq number with adc0 and adc1.
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#
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# To cover this cases, adc_gd32 driver use node-label 'adc0', 'adc1' and
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# 'adc2' to handle gd32 adc irq config directly.
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#
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# Sorry for the restriction, But new added gd32 adc node-label must be 'adc0',
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# 'adc1' and 'adc2'.
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compatible: "gd,gd32-adc"
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include: [adc-controller.yaml, reset-device.yaml, pinctrl-device.yaml]
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properties:
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reg:
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required: true
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resets:
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required: true
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clocks:
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required: true
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rcu-clock-source:
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type: int
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description: |
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Some GD32 ADC have additional clock source, like IRC14M or IRC28M.
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This property used to select the clock and related prescaler, valid
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values defined at 'dts-bindings/adc/gd32xxx.h' headers.
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channels:
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type: int
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description: Number of external channels
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required: true
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interrupts:
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required: true
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"#io-channel-cells":
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const: 1
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pinctrl-0:
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required: true
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pinctrl-names:
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required: true
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io-channel-cells:
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- input
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