54 lines
1.2 KiB
Plaintext
54 lines
1.2 KiB
Plaintext
/*
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* Copyright (c) 2021 The Chromium OS Authors
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* Copyright (c) 2019 Philippe Retornaz <philippe@shapescale.com>
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* Copyright (c) 2019 ST Microelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/g0/stm32g051.dtsi>
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/ {
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soc {
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compatible = "st,stm32g071", "st,stm32g0", "simple-bus";
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usart3: serial@40004800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
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resets = <&rctl STM32_RESET(APB1L, 18U)>;
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interrupts = <29 0>;
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status = "disabled";
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};
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usart4: serial@40004c00 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
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resets = <&rctl STM32_RESET(APB1L, 19U)>;
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interrupts = <29 0>;
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status = "disabled";
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};
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dmamux1: dmamux@40020800 {
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dma-requests= <57>;
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};
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ucpd1: ucpd@4000a000 {
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compatible = "st,stm32-ucpd";
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reg = <0x4000a000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
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interrupts = <8 0>;
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status = "disabled";
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};
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ucpd2: ucpd@4000a400 {
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compatible = "st,stm32-ucpd";
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reg = <0x4000a400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>;
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interrupts = <8 0>;
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status = "disabled";
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};
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};
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};
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