288 lines
7.1 KiB
C
288 lines
7.1 KiB
C
/*
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* Driver for Xilinx AXI Timebase WDT core, as described in
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* Xilinx document PG128.
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*
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* Note that the window mode of operation of the core is
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* currently not supported. Also, only a full SoC reset is
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* supported as a watchdog expiry action.
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*
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* Copyright © 2023 Calian Ltd. All rights reserved.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT xlnx_xps_timebase_wdt_1_00_a
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#include <errno.h>
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/drivers/watchdog.h>
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#include <zephyr/drivers/hwinfo.h>
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enum xilinx_wdt_axi_register {
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REG_TWCSR0 = 0x00, /* Control/Status Register 0 */
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REG_TWCSR1 = 0x04, /* Control/Status Register 1 */
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REG_TBR = 0x08, /* Timebase Register */
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REG_MWR = 0x0C, /* Master Write Control Register */
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};
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enum xilinx_wdt_csr0_bits {
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CSR0_WRS = BIT(3),
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CSR0_WDS = BIT(2),
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CSR0_EWDT1 = BIT(1),
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CSR0_EWDT2 = BIT(0),
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};
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enum xilinx_wdt_csr1_bits {
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CSR1_EWDT2 = BIT(0),
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};
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enum {
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TIMER_WIDTH_MIN = 8,
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};
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LOG_MODULE_REGISTER(wdt_xilinx_axi, CONFIG_WDT_LOG_LEVEL);
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struct xilinx_wdt_axi_config {
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mem_addr_t base;
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uint32_t clock_rate;
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uint8_t timer_width_max;
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bool enable_once;
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};
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struct xilinx_wdt_axi_data {
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struct k_spinlock lock;
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bool timeout_active;
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bool wdt_started;
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};
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static const struct device *first_wdt_dev;
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static int wdt_xilinx_axi_setup(const struct device *dev, uint8_t options)
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{
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const struct xilinx_wdt_axi_config *config = dev->config;
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struct xilinx_wdt_axi_data *data = dev->data;
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k_spinlock_key_t key = k_spin_lock(&data->lock);
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int ret;
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if (!data->timeout_active) {
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ret = -EINVAL;
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goto out;
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}
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if (data->wdt_started) {
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ret = -EBUSY;
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goto out;
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}
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/* We don't actually know or control at the driver level whether
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* the WDT pauses in CPU sleep or when halted by the debugger,
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* so we don't check anything with the options.
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*/
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sys_write32(CSR0_EWDT1 | CSR0_WDS, config->base + REG_TWCSR0);
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sys_write32(CSR1_EWDT2, config->base + REG_TWCSR1);
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data->wdt_started = true;
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ret = 0;
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out:
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k_spin_unlock(&data->lock, key);
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return ret;
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}
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static int wdt_xilinx_axi_disable(const struct device *dev)
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{
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const struct xilinx_wdt_axi_config *config = dev->config;
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struct xilinx_wdt_axi_data *data = dev->data;
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k_spinlock_key_t key = k_spin_lock(&data->lock);
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int ret;
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if (config->enable_once) {
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ret = -EPERM;
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goto out;
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}
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if (!data->wdt_started) {
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ret = -EFAULT;
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goto out;
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}
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sys_write32(CSR0_WDS, config->base + REG_TWCSR0);
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sys_write32(0, config->base + REG_TWCSR1);
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data->wdt_started = false;
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ret = 0;
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out:
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k_spin_unlock(&data->lock, key);
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return ret;
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}
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static int wdt_xilinx_axi_install_timeout(const struct device *dev,
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const struct wdt_timeout_cfg *cfg)
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{
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const struct xilinx_wdt_axi_config *config = dev->config;
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struct xilinx_wdt_axi_data *data = dev->data;
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k_spinlock_key_t key = k_spin_lock(&data->lock);
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uint32_t timer_width;
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bool good_timer_width = false;
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int ret;
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if (data->timeout_active) {
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ret = -ENOMEM;
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goto out;
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}
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if (!(cfg->flags & WDT_FLAG_RESET_SOC)) {
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ret = -ENOTSUP;
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goto out;
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}
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if (cfg->window.min != 0) {
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ret = -EINVAL;
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goto out;
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}
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for (timer_width = TIMER_WIDTH_MIN; timer_width <= config->timer_width_max; timer_width++) {
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/* Note: WDT expiry happens after 2 wraps of the timer (first raises an interrupt
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* which is not used, second triggers a reset) so add 1 to timer_width.
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*/
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const uint64_t expiry_cycles = ((uint64_t)1) << (timer_width + 1);
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const uint64_t expiry_msec = expiry_cycles * 1000 / config->clock_rate;
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if (expiry_msec >= cfg->window.max) {
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LOG_INF("Set timer width to %u, actual expiry %u msec", timer_width,
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(unsigned int)expiry_msec);
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good_timer_width = true;
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break;
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}
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}
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if (!good_timer_width) {
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LOG_ERR("Cannot support timeout value of %u msec", cfg->window.max);
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ret = -EINVAL;
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goto out;
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}
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sys_write32(timer_width, config->base + REG_MWR);
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data->timeout_active = true;
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ret = 0;
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out:
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k_spin_unlock(&data->lock, key);
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return ret;
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}
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static int wdt_xilinx_axi_feed(const struct device *dev, int channel_id)
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{
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const struct xilinx_wdt_axi_config *config = dev->config;
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struct xilinx_wdt_axi_data *data = dev->data;
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k_spinlock_key_t key = k_spin_lock(&data->lock);
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uint32_t twcsr0 = sys_read32(config->base + REG_TWCSR0);
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int ret;
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if (channel_id != 0 || !data->timeout_active) {
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ret = -EINVAL;
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goto out;
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}
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twcsr0 |= CSR0_WDS;
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if (data->wdt_started) {
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twcsr0 |= CSR0_EWDT1;
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}
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sys_write32(twcsr0, config->base + REG_TWCSR0);
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ret = 0;
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out:
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k_spin_unlock(&data->lock, key);
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return ret;
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}
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static int wdt_xilinx_axi_init(const struct device *dev)
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{
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if (IS_ENABLED(CONFIG_WDT_XILINX_AXI_HWINFO_API)) {
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if (first_wdt_dev) {
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LOG_WRN("Multiple WDT instances, only first will implement HWINFO");
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} else {
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first_wdt_dev = dev;
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}
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}
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return 0;
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}
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#ifdef CONFIG_WDT_XILINX_AXI_HWINFO_API
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int z_impl_hwinfo_get_reset_cause(uint32_t *cause)
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{
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if (!first_wdt_dev) {
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return -ENOSYS;
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}
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const struct xilinx_wdt_axi_config *config = first_wdt_dev->config;
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if ((sys_read32(config->base + REG_TWCSR0) & CSR0_WRS) != 0) {
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*cause = RESET_WATCHDOG;
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} else {
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*cause = 0;
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}
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return 0;
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}
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int z_impl_hwinfo_clear_reset_cause(void)
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{
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if (!first_wdt_dev) {
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return -ENOSYS;
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}
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const struct xilinx_wdt_axi_config *config = first_wdt_dev->config;
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struct xilinx_wdt_axi_data *data = first_wdt_dev->data;
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k_spinlock_key_t key = k_spin_lock(&data->lock);
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uint32_t twcsr0 = sys_read32(config->base + REG_TWCSR0);
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if ((twcsr0 & CSR0_WRS) != 0) {
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twcsr0 |= CSR0_WRS;
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sys_write32(twcsr0, config->base + REG_TWCSR0);
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}
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k_spin_unlock(&data->lock, key);
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return 0;
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}
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int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported)
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{
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if (!first_wdt_dev) {
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return -ENOSYS;
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}
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*supported = RESET_WATCHDOG;
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return 0;
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}
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#endif
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static const struct wdt_driver_api wdt_xilinx_api = {
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.setup = wdt_xilinx_axi_setup,
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.disable = wdt_xilinx_axi_disable,
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.install_timeout = wdt_xilinx_axi_install_timeout,
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.feed = wdt_xilinx_axi_feed,
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};
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#define WDT_XILINX_AXI_INIT(inst) \
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static struct xilinx_wdt_axi_data wdt_xilinx_axi_##inst##_dev_data; \
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\
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static const struct xilinx_wdt_axi_config wdt_xilinx_axi_##inst##_cfg = { \
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.base = DT_INST_REG_ADDR(inst), \
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.clock_rate = DT_INST_PROP_BY_PHANDLE(inst, clocks, clock_frequency), \
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.timer_width_max = DT_INST_PROP(inst, xlnx_wdt_interval), \
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.enable_once = DT_INST_PROP(inst, xlnx_wdt_enable_once), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(inst, &wdt_xilinx_axi_init, NULL, &wdt_xilinx_axi_##inst##_dev_data, \
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&wdt_xilinx_axi_##inst##_cfg, PRE_KERNEL_1, \
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &wdt_xilinx_api);
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DT_INST_FOREACH_STATUS_OKAY(WDT_XILINX_AXI_INIT)
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