219 lines
6.5 KiB
C
219 lines
6.5 KiB
C
/*
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* Copyright (c) 2023 by Rivos Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT lowrisc_opentitan_aontimer
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#include <zephyr/kernel.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/drivers/watchdog.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(wdt_opentitan, CONFIG_WDT_LOG_LEVEL);
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#define OT_REG_WDOG_REGWEN_OFFSET 0x10
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#define OT_REG_WDOG_CTRL_OFFSET 0x14
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#define OT_REG_WDOG_BARK_THOLD_OFFSET 0x18
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#define OT_REG_WDOG_BITE_THOLD_OFFSET 0x1C
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#define OT_REG_WDOG_COUNT_OFFSET 0x20
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#define OT_REG_INTR_STATE_OFFSET 0x24
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struct wdt_ot_aontimer_cfg {
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uintptr_t regs;
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uint32_t clk_freq;
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bool wdog_lock;
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};
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struct wdt_ot_aontimer_data {
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wdt_callback_t bark;
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};
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static int ot_aontimer_setup(const struct device *dev, uint8_t options)
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{
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const struct wdt_ot_aontimer_cfg *const cfg = dev->config;
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volatile uintptr_t regs = cfg->regs;
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sys_write32(0, regs + OT_REG_WDOG_COUNT_OFFSET);
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sys_write32(1, regs + OT_REG_WDOG_CTRL_OFFSET);
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if (cfg->wdog_lock) {
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/* Force a read to ensure the timer was enabled. */
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(void) sys_read32(regs + OT_REG_WDOG_CTRL_OFFSET);
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sys_write32(0, regs + OT_REG_WDOG_REGWEN_OFFSET);
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}
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return 0;
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}
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static int ot_aontimer_disable(const struct device *dev)
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{
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const struct wdt_ot_aontimer_cfg *const cfg = dev->config;
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volatile uintptr_t regs = cfg->regs;
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if (!sys_read32(regs + OT_REG_WDOG_REGWEN_OFFSET)) {
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LOG_ERR("Cannot disable - watchdog settings locked.");
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return -EPERM;
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}
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uint32_t ctrl_val = sys_read32(regs + OT_REG_WDOG_CTRL_OFFSET);
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if (!(ctrl_val & BIT(0))) {
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return -EFAULT;
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}
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sys_write32(ctrl_val & ~BIT(0), regs + OT_REG_WDOG_CTRL_OFFSET);
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return 0;
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}
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/*
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* The OpenTitan AON Timer includes a multi-level watchdog timer.
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* While the first stage supports an interrupt callback, the second does not.
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* The second stage is mandatory to adjust the "bite" time window.
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*
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* Some boundaries are enforced to prevent behavior that is technically correct
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* but is not likely intended.
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* Bark:
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* Minimum must be 0. Maximum must be > min.
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* The bark interrupt occurs at max (or if the timeout is too long to be
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* supported, the value x s.t. min < x < max and x is the largest valid timeout)
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* Bite:
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* Minimum must be >= bark.min, and maximum >= bark.max. If the timeout is too
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* long to fit, it tries to find the value x s.t. min < x < max where x is the
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* largest valid timeout.
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* The bite action occurs max.
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*/
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static int ot_aontimer_install_timeout(const struct device *dev,
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const struct wdt_timeout_cfg *cfg)
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{
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struct wdt_ot_aontimer_data *data = dev->data;
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const struct wdt_ot_aontimer_cfg *const dev_cfg = dev->config;
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volatile uintptr_t reg_base = dev_cfg->regs;
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const uint64_t max_window = (uint64_t) UINT32_MAX * 1000 / dev_cfg->clk_freq;
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uint64_t bite_thold;
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#ifdef CONFIG_WDT_MULTISTAGE
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/* When multistage is selected, add an intermediate bark stage */
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uint64_t bark_thold;
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struct wdt_timeout_cfg *bite = cfg->next;
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if (bite == NULL || bite->window.max < cfg->window.max ||
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(uint64_t) bite->window.min > max_window) {
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return -EINVAL;
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}
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/*
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* Flag must be clear for stage 1, and reset SOC for stage 2.
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* CPU not supported
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*/
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if (cfg->flags != WDT_FLAG_RESET_NONE || bite->flags != WDT_FLAG_RESET_SOC) {
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return -ENOTSUP;
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}
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#endif
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if (cfg->window.min > cfg->window.max || (uint64_t) cfg->window.min > max_window) {
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return -EINVAL;
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}
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if (!sys_read32(reg_base + OT_REG_WDOG_REGWEN_OFFSET)) {
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LOG_ERR("Cannot install timeout - watchdog settings locked.");
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return -ENOMEM;
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}
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/* Watchdog is already enabled! */
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if (sys_read32(reg_base + OT_REG_WDOG_CTRL_OFFSET) & BIT(0)) {
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return -EBUSY;
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}
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#ifdef CONFIG_WDT_MULTISTAGE
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/* Force 64-bit ops to ensure thresholds fits in the timer reg. */
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bark_thold = ((uint64_t) cfg->window.max * dev_cfg->clk_freq / 1000);
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bite_thold = ((uint64_t) bite->window.max * dev_cfg->clk_freq / 1000);
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/* Saturate these config values; min is verified to be < max_window */
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if (bark_thold > UINT32_MAX) {
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bark_thold = UINT32_MAX;
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}
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if (bite_thold > UINT32_MAX) {
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bite_thold = UINT32_MAX;
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}
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data->bark = cfg->callback;
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sys_write32((uint32_t) bark_thold, reg_base + OT_REG_WDOG_BARK_THOLD_OFFSET);
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sys_write32((uint32_t) bite_thold, reg_base + OT_REG_WDOG_BITE_THOLD_OFFSET);
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#else
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bite_thold = ((uint64_t) cfg->window.max * dev_cfg->clk_freq / 1000);
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/* Saturate this config value; min is verified to be < max_window */
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if (bite_thold > UINT32_MAX) {
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bite_thold = UINT32_MAX;
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}
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if (cfg->flags == WDT_FLAG_RESET_NONE) {
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/* Set bite -> bark, so we generate an interrupt instead of resetting */
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sys_write32((uint32_t) bite_thold, reg_base + OT_REG_WDOG_BARK_THOLD_OFFSET);
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/* Disable bite by writing it to max. Edge case is the bark = max. */
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sys_write32(UINT32_MAX, reg_base + OT_REG_WDOG_BITE_THOLD_OFFSET);
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data->bark = cfg->callback;
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} else {
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data->bark = NULL;
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/* Effectively disable bark by setting it to max */
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sys_write32(UINT32_MAX, reg_base + OT_REG_WDOG_BARK_THOLD_OFFSET);
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sys_write32((uint32_t) bite_thold, reg_base + OT_REG_WDOG_BITE_THOLD_OFFSET);
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}
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#endif
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return 0;
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}
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static int ot_aontimer_feed(const struct device *dev, int channel_id)
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{
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ARG_UNUSED(channel_id);
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const struct wdt_ot_aontimer_cfg *const cfg = dev->config;
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volatile uintptr_t regs = cfg->regs;
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sys_write32(0, regs + OT_REG_WDOG_COUNT_OFFSET);
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/* Deassert the interrupt line */
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sys_write32(BIT(1), regs + OT_REG_INTR_STATE_OFFSET);
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return 0;
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}
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static void wdt_ot_isr(const struct device *dev)
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{
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const struct wdt_ot_aontimer_cfg *const cfg = dev->config;
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struct wdt_ot_aontimer_data *data = dev->data;
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volatile uintptr_t regs = cfg->regs;
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if (data->bark != NULL) {
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data->bark(dev, 0);
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}
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/* Deassert the interrupt line */
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sys_write32(BIT(1), regs + OT_REG_INTR_STATE_OFFSET);
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}
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static int ot_aontimer_init(const struct device *dev)
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{
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IRQ_CONNECT(
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DT_INST_IRQ_BY_IDX(0, 0, irq),
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DT_INST_IRQ_BY_IDX(0, 0, priority), wdt_ot_isr,
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DEVICE_DT_INST_GET(0), 0);
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irq_enable(DT_INST_IRQ_BY_IDX(0, 0, irq));
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return 0;
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}
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static struct wdt_ot_aontimer_data ot_aontimer_data;
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static struct wdt_ot_aontimer_cfg ot_aontimer_cfg = {
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.regs = (volatile uintptr_t) DT_INST_REG_ADDR(0),
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.clk_freq = DT_INST_PROP(0, clock_frequency),
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.wdog_lock = DT_INST_PROP(0, wdog_lock),
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};
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static const struct wdt_driver_api ot_aontimer_api = {
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.setup = ot_aontimer_setup,
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.disable = ot_aontimer_disable,
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.install_timeout = ot_aontimer_install_timeout,
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.feed = ot_aontimer_feed,
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};
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DEVICE_DT_INST_DEFINE(0, ot_aontimer_init, NULL,
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&ot_aontimer_data, &ot_aontimer_cfg, PRE_KERNEL_1,
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&ot_aontimer_api);
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