272 lines
7.7 KiB
C
272 lines
7.7 KiB
C
/*
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* Copyright (c) 2023 Analog Devices, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT adi_max32_watchdog
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#include <zephyr/drivers/watchdog.h>
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#include <zephyr/irq.h>
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#include <zephyr/drivers/clock_control/adi_max32_clock_control.h>
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#include <soc.h>
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#include <errno.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(wdt_max32, CONFIG_WDT_LOG_LEVEL);
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#include <wrap_max32_wdt.h>
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struct max32_wdt_config {
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mxc_wdt_regs_t *regs;
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const struct device *clock;
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struct max32_perclk perclk;
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void (*irq_func)(void);
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};
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struct max32_wdt_data {
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struct wdt_window timeout;
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wdt_callback_t callback;
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};
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static int wdt_max32_calculate_timeout(uint32_t timeout, uint32_t clock_src)
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{
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int i;
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uint32_t clk_frequency = 0;
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uint32_t number_of_tick = 0;
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clk_frequency = ADI_MAX32_GET_PRPH_CLK_FREQ(clock_src);
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if (clk_frequency == 0) {
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LOG_ERR("Unsupported clock source.");
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return -ENOTSUP;
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}
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number_of_tick = ((uint64_t)timeout * (uint64_t)clk_frequency) / 1000;
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i = LOG2CEIL(number_of_tick); /* Find closest bigger 2^i value than number_of_tick. */
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i = CLAMP(i, 16, 31); /* Limit i between 16 and 31. */
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/* It returns 31 - i because period thresholds are inverse ordered in register. */
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return (31 - i);
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}
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static int wdt_max32_disable(const struct device *dev)
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{
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const struct max32_wdt_config *cfg = dev->config;
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if (!(cfg->regs->ctrl & WRAP_MXC_F_WDT_CTRL_EN)) {
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return -EFAULT;
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}
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MXC_WDT_Disable(cfg->regs);
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return 0;
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}
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static int wdt_max32_feed(const struct device *dev, int channel_id)
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{
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ARG_UNUSED(channel_id);
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const struct max32_wdt_config *cfg = dev->config;
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MXC_WDT_ResetTimer(cfg->regs);
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return 0;
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}
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static int wdt_max32_setup(const struct device *dev, uint8_t options)
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{
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const struct max32_wdt_config *cfg = dev->config;
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if (cfg->regs->ctrl & WRAP_MXC_F_WDT_CTRL_EN) {
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return -EBUSY;
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}
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if (options & WDT_OPT_PAUSE_IN_SLEEP) {
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return -ENOTSUP;
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}
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MXC_WDT_ResetTimer(cfg->regs);
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MXC_WDT_Enable(cfg->regs);
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return 0;
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}
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static int wdt_max32_install_timeout(const struct device *dev, const struct wdt_timeout_cfg *cfg)
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{
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int ret = 0;
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const struct max32_wdt_config *dev_cfg = dev->config;
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struct max32_wdt_data *data = dev->data;
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mxc_wdt_regs_t *regs = dev_cfg->regs;
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wrap_mxc_wdt_cfg_t wdt_cfg;
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if (cfg->window.max == 0U) {
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return -EINVAL;
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}
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if (regs->ctrl & WRAP_MXC_F_WDT_CTRL_EN) {
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return -EBUSY;
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}
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data->timeout = cfg->window;
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data->callback = cfg->callback;
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/* Default values to eliminate warnings */
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wdt_cfg.mode = MXC_WDT_COMPATIBILITY;
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wdt_cfg.upperResetPeriod = 0;
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wdt_cfg.lowerResetPeriod = 0;
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wdt_cfg.upperIntPeriod = 0;
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wdt_cfg.lowerIntPeriod = 0;
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if (data->timeout.min > 0) {
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wdt_cfg.mode = MXC_WDT_WINDOWED;
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ret = Wrap_MXC_WDT_Init(regs, &wdt_cfg);
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if (ret != E_NO_ERROR) {
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LOG_DBG("%s does not support windowed mode.", CONFIG_BOARD);
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return -EINVAL;
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}
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int lower_timeout_period =
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wdt_max32_calculate_timeout(data->timeout.min, dev_cfg->perclk.clk_src);
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if (lower_timeout_period == -ENOTSUP) {
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return -EINVAL;
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}
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if (data->callback == NULL) {
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wdt_cfg.lowerResetPeriod = lower_timeout_period;
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wdt_cfg.lowerIntPeriod = lower_timeout_period; /* Not used */
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} else {
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switch (lower_timeout_period) {
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case MXC_WDT_PERIOD_2_16: /* Min timeout */
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wdt_cfg.lowerResetPeriod = MXC_WDT_PERIOD_2_17;
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wdt_cfg.lowerIntPeriod = MXC_WDT_PERIOD_2_16;
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break;
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default:
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/* Generate interrupt just before reset */
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wdt_cfg.lowerResetPeriod = lower_timeout_period;
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/* +1 means one steps before */
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wdt_cfg.lowerIntPeriod = lower_timeout_period + 1;
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break;
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}
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}
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}
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int upper_timeout_period =
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wdt_max32_calculate_timeout(data->timeout.max, dev_cfg->perclk.clk_src);
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if (upper_timeout_period == -ENOTSUP) {
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return -EINVAL;
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}
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if (data->callback == NULL) {
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wdt_cfg.upperResetPeriod = upper_timeout_period;
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wdt_cfg.upperIntPeriod = upper_timeout_period; /* Not used */
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} else {
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switch (upper_timeout_period) {
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case MXC_WDT_PERIOD_2_16: /* Min timeout */
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wdt_cfg.upperResetPeriod = MXC_WDT_PERIOD_2_17;
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wdt_cfg.upperIntPeriod = MXC_WDT_PERIOD_2_16;
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break;
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default:
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/* Generate interrupt just before reset */
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wdt_cfg.upperResetPeriod = upper_timeout_period;
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/* +1 means one steps before */
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wdt_cfg.upperIntPeriod = upper_timeout_period + 1;
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break;
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}
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}
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Wrap_MXC_WDT_SetResetPeriod(regs, &wdt_cfg);
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switch (cfg->flags) {
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case WDT_FLAG_RESET_SOC:
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MXC_WDT_EnableReset(regs);
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LOG_DBG("Configuring reset SOC mode.");
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break;
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case WDT_FLAG_RESET_NONE:
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MXC_WDT_DisableReset(regs);
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LOG_DBG("Configuring non-reset mode.");
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break;
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default:
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LOG_ERR("Unsupported watchdog config flag.");
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return -ENOTSUP;
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}
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/* If callback is not null, enable interrupt. */
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if (data->callback) {
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Wrap_MXC_WDT_SetIntPeriod(regs, &wdt_cfg);
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MXC_WDT_EnableInt(regs);
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}
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return ret;
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}
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static void wdt_max32_isr(const void *param)
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{
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const struct device *dev = (const struct device *)param;
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const struct max32_wdt_config *cfg = dev->config;
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struct max32_wdt_data *data = dev->data;
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if (data->callback) {
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data->callback(dev, 0);
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}
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MXC_WDT_ClearIntFlag(cfg->regs);
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}
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static int wdt_max32_init(const struct device *dev)
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{
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int ret = 0;
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const struct max32_wdt_config *cfg = dev->config;
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mxc_wdt_regs_t *regs = cfg->regs;
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/* Enable clock */
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ret = clock_control_on(cfg->clock, (clock_control_subsys_t)&cfg->perclk);
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if (ret) {
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return ret;
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}
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ret = Wrap_MXC_WDT_SelectClockSource(regs, cfg->perclk.clk_src);
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if (ret != E_NO_ERROR) {
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LOG_ERR("WDT instance does not support given clock source.");
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return -ENOTSUP;
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}
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/* Disable all actions */
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MXC_WDT_Disable(regs);
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MXC_WDT_DisableReset(regs);
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MXC_WDT_DisableInt(regs);
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MXC_WDT_ClearResetFlag(regs);
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MXC_WDT_ClearIntFlag(regs);
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cfg->irq_func(); /* WDT IRQ enable*/
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return 0;
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}
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static const struct wdt_driver_api max32_wdt_api = {.setup = wdt_max32_setup,
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.disable = wdt_max32_disable,
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.install_timeout = wdt_max32_install_timeout,
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.feed = wdt_max32_feed};
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#define MAX32_WDT_INIT(_num) \
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static void wdt_max32_irq_init_##_num(void) \
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{ \
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IRQ_CONNECT(DT_INST_IRQN(_num), DT_INST_IRQ(_num, priority), wdt_max32_isr, \
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DEVICE_DT_INST_GET(_num), 0); \
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irq_enable(DT_INST_IRQN(_num)); \
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} \
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static struct max32_wdt_data max32_wdt_data##_num; \
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static const struct max32_wdt_config max32_wdt_config##_num = { \
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.regs = (mxc_wdt_regs_t *)DT_INST_REG_ADDR(_num), \
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.clock = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(_num)), \
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.perclk.clk_src = \
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DT_INST_PROP_OR(_num, clock_source, ADI_MAX32_PRPH_CLK_SRC_PCLK), \
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.perclk.bus = DT_INST_CLOCKS_CELL(_num, offset), \
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.perclk.bit = DT_INST_CLOCKS_CELL(_num, bit), \
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.irq_func = &wdt_max32_irq_init_##_num, \
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}; \
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DEVICE_DT_INST_DEFINE(_num, wdt_max32_init, NULL, &max32_wdt_data##_num, \
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&max32_wdt_config##_num, POST_KERNEL, \
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &max32_wdt_api);
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DT_INST_FOREACH_STATUS_OKAY(MAX32_WDT_INIT)
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