225 lines
7.2 KiB
C
225 lines
7.2 KiB
C
/* spi_pw.h - Penwell SPI driver definitions */
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/*
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* Copyright (c) 2023 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_SPI_SPI_PW_H_
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#define ZEPHYR_DRIVERS_SPI_SPI_PW_H_
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#include "spi_context.h"
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/* lpss penwell spi registers */
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#define PW_SPI_REG_CTRLR0 0x00
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#define PW_SPI_REG_CTRLR1 0x04
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#define PW_SPI_REG_SSSR 0x08
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#define PW_SPI_REG_SSDR 0x10
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#define PW_SPI_REG_SSTO 0x28
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#define PW_SPI_REG_SITF 0x44
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#define PW_SPI_REG_SIRF 0x48
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#define PW_SPI_REG_CLKS 0x200
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#define PW_SPI_REG_RESETS 0x204
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#define PW_SPI_REG_ACTIVE_LTR 0x210
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#define PW_SPI_REG_IDLE_LTR 0x217
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#define PW_SPI_REG_TX_BIT_COUNT 0x218
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#define PW_SPI_REG_RX_BIT_COUNT 0x21c
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#define PW_SPI_REG_DMA_FINISH_DIS 0x220
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#define PW_SPI_REG_CS_CTRL 0x224
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#define PW_SPI_REG_SW_SCRATCH 0x228
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#define PW_SPI_REG_CLK_GATE 0x238
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#define PW_SPI_REG_REMAP_ADDR_LO 0x240
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#define PW_SPI_REG_REMAP_ADDR_HI 0x244
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#define PW_SPI_REG_DEV_IDLE_CTRL 0x24c
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#define PW_SPI_REG_DEL_RX_CLK 0x250
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#define PW_SPI_REG_CAP 0x2fc
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/* CTRLR0 settings */
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#define PW_SPI_CTRLR0_SSE_BIT BIT(7)
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#define PW_SPI_CTRLR0_EDSS_BIT BIT(20)
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#define PW_SPI_CTRLR0_RIM_BIT BIT(22)
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#define PW_SPI_CTRLR0_TIM_BIT BIT(23)
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#define PW_SPI_CTRLR0_MOD_BIT BIT(31)
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#define PW_SPI_CTRLR0_DATA_MASK (~(0xf << 0))
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#define PW_SPI_CTRLR0_EDSS_MASK (~(0x1 << 20))
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/* Data size set bits sscr0[3:0] */
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#define PW_SPI_DATA_SIZE_4_BIT 0x3
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#define PW_SPI_DATA_SIZE_8_BIT 0x7
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#define PW_SPI_DATA_SIZE_16_BIT 0xf
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#define PW_SPI_DATA_SIZE_32_BIT (PW_SPI_CTRLR0_EDSS_BIT | \
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PW_SPI_DATA_SIZE_16_BIT)
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/* Frame format sscr0[5:4] */
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#define PW_SPI_FRF_MOTOROLA (~(0x3 << 4))
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/* SSP Baud rate sscr0[19:8] */
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#define PW_SPI_BR_2MHZ 0x31
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#define PW_SPI_BR_4MHZ 0x18
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#define PW_SPI_BR_5MHZ 0x13
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#define PW_SPI_BR_10MHZ 0x9
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#define PW_SPI_BR_20MHZ 0x5
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#define PW_SPI_BR_MAX_FRQ 20000000 /* 20 MHz */
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/* [19:8] 12 bits */
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#define PW_SPI_SCR_MASK (BIT_MASK(12) << 8)
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#define PW_SPI_SCR_SHIFT 0x8
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/* CTRLR1 settings */
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#define PW_SPI_CTRL1_RIE_BIT BIT(0)
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#define PW_SPI_CTRL1_TIE_BIT BIT(1)
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#define PW_SPI_CTRL1_LBM_BIT BIT(2)
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#define PW_SPI_CTRL1_SPO_BIT BIT(3)
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#define PW_SPI_CTRL1_SPH_BIT BIT(4)
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#define PW_SPI_CTRL1_IFS_BIT BIT(16)
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#define PW_SPI_CTRL1_TINTE_BIT BIT(19)
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#define PW_SPI_CTRL1_RSRE_BIT BIT(20)
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#define PW_SPI_CTRL1_TSRE_BIT BIT(21)
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#define PW_SPI_CTRL1_TRAIL_BIT BIT(22)
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#define PW_SPI_CTRL1_RWOT_BIT BIT(23)
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/* [4:3] phase & polarity mask */
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#define PW_SPI_CTRL1_SPO_SPH_MASK (BIT_MASK(2) << 3)
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/* Status Register */
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#define PW_SPI_SSSR_TNF_BIT BIT(2)
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#define PW_SPI_SSSR_RNE_BIT BIT(3)
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#define PW_SPI_SSSR_BSY_BIT BIT(4)
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#define PW_SPI_SSSR_TFS_BIT BIT(5)
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#define PW_SPI_SSSR_RFS_BIT BIT(6)
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#define PW_SPI_SSSR_ROR_BIT BIT(7)
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#define PW_SPI_SSSR_PINT_BIT BIT(18)
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#define PW_SPI_SSSR_TINT_BIT BIT(19)
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#define PW_SPI_SSSR_TUR_BIT BIT(21)
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/* SPI Tx FIFO Higher Water Mark [5:0] */
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#define PW_SPI_SITF_HWM_1_ENTRY 0x1
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#define PW_SPI_SITF_HWM_4_ENTRY 0x4
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#define PW_SPI_SITF_HWM_8_ENTRY 0x8
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#define PW_SPI_SITF_HWM_16_ENTRY 0x10
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#define PW_SPI_SITF_HWM_32_ENTRY 0x20
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#define PW_SPI_SITF_HWM_64_ENTRY 0x40
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/* SPI Tx FIFO Lower Water Mark[13:8] */
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#define PW_SPI_SITF_LWM_2_ENTRY (BIT(0) << 8)
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#define PW_SPI_SITF_LWM_3_ENTRY (BIT(1) << 8)
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#define PW_SPI_SITF_LWM_4_ENTRY ((BIT(1) | BIT(0)) << 8)
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/* SPI Tx FIFO Level SITF[21:16] */
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#define PW_SPI_SITF_SITFL_MASK (BIT_MASK(6) << 16)
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#define PW_SPI_SITF_SITFL_SHIFT 0x10
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/* SPI Rx FIFO water mark */
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#define PW_SPI_SIRF_WMRF_1_ENTRY 0x1
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#define PW_SPI_SIRF_WMRF_2_ENTRY 0x2
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#define PW_SPI_SIRF_WMRF_4_ENTRY 0x4
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#define PW_SPI_SITF_WMRF_8_ENTRY 0x8
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#define PW_SPI_SITF_WMRF_16_ENTRY 0x10
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#define PW_SPI_SITF_WMRF_32_ENTRY 0x20
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#define PW_SPI_SITF_WMRF_64_ENTRY 0x40
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/* SPI Rx FIFO Level RITF[13:8] */
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#define PW_SPI_SIRF_SIRFL_MASK (BIT_MASK(6) << 8)
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#define PW_SPI_SIRF_SIRFL_SHIFT 0x8
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/* Threshold default value */
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#define PW_SPI_WM_MASK BIT_MASK(6)
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#define PW_SPI_SITF_LWMTF_SHIFT 0x8
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#define PW_SPI_SITF_LOW_WM_DFLT BIT(PW_SPI_SITF_LWMTF_SHIFT)
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#define PW_SPI_SITF_HIGH_WM_DFLT 0x20
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#define PW_SPI_SIRF_WM_DFLT 0x28
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/* Clocks */
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#define PW_SPI_CLKS_EN_BIT BIT(0)
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#define PW_SPI_CLKS_MVAL BIT(1)
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#define PW_SPI_CLKS_NVAL BIT(16)
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#define PW_SPI_CLKS_UPDATE_BIT BIT(31)
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/* mval mask [15:1] */
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#define PW_SPI_CLKS_MVAL_MASK (BIT_MASK(15) << 1)
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/* nval mask [30:16] */
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#define PW_SPI_CLKS_NVAL_MASK (BIT_MASK(15) << 16)
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/* SPI chip select control */
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#define PW_SPI_CS_MODE_BIT 0
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#define PW_SPI_CS_STATE_BIT 1
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#define PW_SPI_CS0_POL_BIT 12
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#define PW_SPI_CS1_POL_BIT 13
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/* ssp interrupt error bits */
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#define PW_SPI_INTR_ERRORS_MASK (PW_SPI_SSSR_TUR_BIT | \
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PW_SPI_SSSR_ROR_BIT | \
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PW_SPI_SSSR_TINT_BIT)
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/* ssp interrupt bits */
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#define PW_SPI_INTR_BITS (PW_SPI_CTRL1_TIE_BIT | \
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PW_SPI_CTRL1_RIE_BIT | \
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PW_SPI_CTRL1_TINTE_BIT)
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#define PW_SPI_INTR_MASK_TX (~(PW_SPI_CTRL1_TIE_BIT | \
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PW_SPI_CTRL1_TINTE_BIT))
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#define PW_SPI_INTR_MASK_RX (PW_SPI_CTRL1_RIE_BIT)
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/* SSP & DMA reset */
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#define PW_SPI_INST_RESET 0x7
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/* Chip select control */
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#define PW_SPI_CS_CTRL_SW_MODE BIT(0)
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#define PW_SPI_CS_HIGH BIT(1)
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#define PW_SPI_CS_LOW (~(PW_SPI_CS_HIGH))
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#define PW_SPI_CS_CTRL_CS_MASK 0x3
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#define PW_SPI_CS_EN_SHIFT 0x8
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#define PW_SPI_CS0_SELECT (~(BIT(PW_SPI_CS_EN_SHIFT)))
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#define PW_SPI_CS1_SELECT BIT(PW_SPI_CS_EN_SHIFT)
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#define PW_SPI_CS_CTRL_HW_MODE (~(PW_SPI_CS_CTRL_SW_MODE))
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#define PW_SPI_WIDTH_8BITS 8
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#define PW_SPI_FRAME_SIZE_1_BYTE 1
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#define PW_SPI_FRAME_SIZE_2_BYTES 2
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#define PW_SPI_FRAME_SIZE_4_BYTES 4
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#define PW_SPI_CS1_OUTPUT_SELECT 1
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enum spi_pw_spo_sph_mode {
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SPI_PW_MODE0 = 0,
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SPI_PW_MODE1,
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SPI_PW_MODE2,
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SPI_PW_MODE3,
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};
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enum spi_pw_cs_mode {
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CS_HW_MODE = 0,
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CS_SW_MODE,
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CS_GPIO_MODE,
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};
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struct spi_pw_config {
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uint32_t id;
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#ifdef CONFIG_SPI_PW_INTERRUPT
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void (*irq_config)(const struct device *dev);
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#endif
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uint32_t clock_freq;
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uint8_t op_modes;
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#if DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie)
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struct pcie_dev *pcie;
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#endif
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};
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struct spi_pw_data {
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DEVICE_MMIO_RAM;
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struct spi_context ctx;
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uint8_t dfs;
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uint8_t fifo_diff;
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uint8_t cs_mode;
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uint8_t cs_output;
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uint32_t id;
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uint8_t fifo_depth;
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};
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#endif /* ZEPHYR_DRIVERS_SPI_SPI_PW_H_ */
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