451 lines
14 KiB
C
451 lines
14 KiB
C
/*
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* Copyright (c) 2024 Nuvoton Technology Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nuvoton_npcx_spip
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#include <zephyr/drivers/spi.h>
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#include <zephyr/drivers/spi/rtio.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/kernel.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(spi_npcx_spip, CONFIG_SPI_LOG_LEVEL);
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#include "spi_context.h"
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/* Transfer this NOP value when tx buf is null */
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#define SPI_NPCX_SPIP_TX_NOP 0x00
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#define SPI_NPCX_SPIP_WAIT_STATUS_TIMEOUT_US 1000
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/* The max allowed prescaler divider */
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#define SPI_NPCX_MAX_PRESCALER_DIV INT8_MAX
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struct spi_npcx_spip_data {
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struct spi_context ctx;
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uint32_t src_clock_freq;
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uint8_t bytes_per_frame;
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};
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struct spi_npcx_spip_cfg {
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struct spip_reg *reg_base;
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struct npcx_clk_cfg clk_cfg;
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#ifdef CONFIG_SPI_NPCX_SPIP_INTERRUPT
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/* routine for configuring SPIP ISR */
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void (*irq_cfg_func)(const struct device *dev);
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#endif
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const struct pinctrl_dev_config *pcfg;
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};
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static int spi_npcx_spip_configure(const struct device *dev, const struct spi_config *spi_cfg)
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{
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uint8_t prescaler_divider;
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const struct spi_npcx_spip_cfg *const config = dev->config;
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struct spi_npcx_spip_data *const data = dev->data;
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struct spip_reg *const reg_base = config->reg_base;
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spi_operation_t operation = spi_cfg->operation;
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uint8_t frame_size;
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if (spi_context_configured(&data->ctx, spi_cfg)) {
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/* This configuration is already in use */
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return 0;
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}
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if (operation & SPI_HALF_DUPLEX) {
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LOG_ERR("Half duplex mode is not supported");
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return -ENOTSUP;
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}
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if (SPI_OP_MODE_GET(operation) != SPI_OP_MODE_MASTER) {
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LOG_ERR("Only SPI controller mode is supported");
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return -ENOTSUP;
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}
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if (operation & SPI_MODE_LOOP) {
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LOG_ERR("Loopback mode is not supported");
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return -ENOTSUP;
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}
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/*
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* If the GPIO CS configuration is not present, return error because the hardware CS is
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* not supported.
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*/
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if (!spi_cs_is_gpio(spi_cfg)) {
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LOG_ERR("Only GPIO CS is supported");
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return -ENOTSUP;
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}
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/* Get the frame length */
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frame_size = SPI_WORD_SIZE_GET(operation);
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if (frame_size == 8) {
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data->bytes_per_frame = 1;
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reg_base->SPIP_CTL1 &= ~BIT(NPCX_SPIP_CTL1_MOD);
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} else if (frame_size == 16) {
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reg_base->SPIP_CTL1 |= BIT(NPCX_SPIP_CTL1_MOD);
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data->bytes_per_frame = 2;
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} else {
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LOG_ERR("Only support word sizes either 8 or 16 bits");
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return -ENOTSUP;
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}
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if (IS_ENABLED(CONFIG_SPI_EXTENDED_MODES) &&
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(operation & SPI_LINES_MASK) != SPI_LINES_SINGLE) {
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LOG_ERR("Only single line mode is supported");
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return -ENOTSUP;
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}
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/* Set the endianness */
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if (operation & SPI_TRANSFER_LSB) {
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LOG_ERR("Shift out with LSB is not supported");
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return -ENOTSUP;
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}
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/*
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* Set CPOL and CPHA.
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* The following is how to map npcx spip control register to CPOL and CPHA
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* CPOL CPHA | SCIDL SCM
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* -----------------------------
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* 0 0 | 0 0
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* 0 1 | 0 1
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* 1 0 | 1 1
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* 1 1 | 1 0
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*/
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if (operation & SPI_MODE_CPOL) {
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reg_base->SPIP_CTL1 |= BIT(NPCX_SPIP_CTL1_SCIDL);
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} else {
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reg_base->SPIP_CTL1 &= ~BIT(NPCX_SPIP_CTL1_SCIDL);
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}
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if (((operation & SPI_MODE_CPOL) == SPI_MODE_CPOL) !=
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((operation & SPI_MODE_CPHA) == SPI_MODE_CPHA)) {
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reg_base->SPIP_CTL1 |= BIT(NPCX_SPIP_CTL1_SCM);
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} else {
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reg_base->SPIP_CTL1 &= ~BIT(NPCX_SPIP_CTL1_SCM);
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}
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/* Set the SPI frequency */
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prescaler_divider = data->src_clock_freq / 2 / spi_cfg->frequency;
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if (prescaler_divider >= 1) {
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prescaler_divider -= 1;
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}
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if (prescaler_divider >= SPI_NPCX_MAX_PRESCALER_DIV) {
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LOG_ERR("SPI divider %d exceeds the max allowed value %d.", prescaler_divider,
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SPI_NPCX_MAX_PRESCALER_DIV);
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return -ENOTSUP;
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}
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SET_FIELD(reg_base->SPIP_CTL1, NPCX_SPIP_CTL1_SCDV, prescaler_divider);
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data->ctx.config = spi_cfg;
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return 0;
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}
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static void spi_npcx_spip_process_tx_buf(struct spi_npcx_spip_data *const data, uint16_t *tx_frame)
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{
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/* Get the tx_frame from tx_buf only when tx_buf != NULL */
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if (spi_context_tx_buf_on(&data->ctx)) {
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if (data->bytes_per_frame == 1) {
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*tx_frame = UNALIGNED_GET((uint8_t *)(data->ctx.tx_buf));
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} else {
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*tx_frame = UNALIGNED_GET((uint16_t *)(data->ctx.tx_buf));
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}
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}
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/*
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* The update is ignored if TX is off (tx_len == 0).
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* Note: if tx_buf == NULL && tx_len != 0, the update still counts.
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*/
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spi_context_update_tx(&data->ctx, data->bytes_per_frame, 1);
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}
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static void spi_npcx_spip_process_rx_buf(struct spi_npcx_spip_data *const data, uint16_t rx_frame)
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{
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if (spi_context_rx_buf_on(&data->ctx)) {
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if (data->bytes_per_frame == 1) {
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UNALIGNED_PUT(rx_frame, (uint8_t *)data->ctx.rx_buf);
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} else {
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UNALIGNED_PUT(rx_frame, (uint16_t *)data->ctx.rx_buf);
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}
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}
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spi_context_update_rx(&data->ctx, data->bytes_per_frame, 1);
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}
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#ifndef CONFIG_SPI_NPCX_SPIP_INTERRUPT
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static int spi_npcx_spip_xfer_frame(const struct device *dev)
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{
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const struct spi_npcx_spip_cfg *const config = dev->config;
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struct spip_reg *const reg_base = config->reg_base;
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struct spi_npcx_spip_data *const data = dev->data;
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uint16_t tx_frame = SPI_NPCX_SPIP_TX_NOP;
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uint16_t rx_frame;
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spi_npcx_spip_process_tx_buf(data, &tx_frame);
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if (WAIT_FOR(!IS_BIT_SET(reg_base->SPIP_STAT, NPCX_SPIP_STAT_BSY),
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SPI_NPCX_SPIP_WAIT_STATUS_TIMEOUT_US, NULL) == false) {
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LOG_ERR("Check Status BSY Timeout");
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return -ETIMEDOUT;
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}
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reg_base->SPIP_DATA = tx_frame;
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if (WAIT_FOR(IS_BIT_SET(reg_base->SPIP_STAT, NPCX_SPIP_STAT_RBF),
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SPI_NPCX_SPIP_WAIT_STATUS_TIMEOUT_US, NULL) == false) {
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LOG_ERR("Check Status RBF Timeout");
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return -ETIMEDOUT;
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}
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rx_frame = reg_base->SPIP_DATA;
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spi_npcx_spip_process_rx_buf(data, rx_frame);
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return 0;
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}
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#endif
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static bool spi_npcx_spip_transfer_ongoing(struct spi_npcx_spip_data *data)
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{
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return spi_context_tx_on(&data->ctx) || spi_context_rx_on(&data->ctx);
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}
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#ifdef CONFIG_SPI_NPCX_SPIP_INTERRUPT
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static void spi_npcx_spip_isr(const struct device *dev)
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{
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const struct spi_npcx_spip_cfg *const config = dev->config;
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struct spip_reg *const reg_base = config->reg_base;
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struct spi_npcx_spip_data *const data = dev->data;
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struct spi_context *ctx = &data->ctx;
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uint16_t tx_frame = SPI_NPCX_SPIP_TX_NOP;
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uint16_t rx_frame;
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uint8_t status;
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status = reg_base->SPIP_STAT;
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if (!IS_BIT_SET(status, NPCX_SPIP_STAT_BSY) && !IS_BIT_SET(status, NPCX_SPIP_STAT_RBF)) {
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reg_base->SPIP_CTL1 &= ~BIT(NPCX_SPIP_CTL1_EIW);
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spi_npcx_spip_process_tx_buf(data, &tx_frame);
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reg_base->SPIP_DATA = tx_frame;
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} else if (IS_BIT_SET(status, NPCX_SPIP_STAT_RBF)) {
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rx_frame = reg_base->SPIP_DATA;
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spi_npcx_spip_process_rx_buf(data, rx_frame);
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if (!spi_npcx_spip_transfer_ongoing(data)) {
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reg_base->SPIP_CTL1 &= ~BIT(NPCX_SPIP_CTL1_EIR);
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/*
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* The CS might not de-assert if SPI_HOLD_ON_CS is configured.
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* In this case, CS de-assertion reles on the caller to explicitly call
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* spi_release() API.
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*/
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spi_context_cs_control(ctx, false);
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spi_context_complete(ctx, dev, 0);
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} else {
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spi_npcx_spip_process_tx_buf(data, &tx_frame);
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reg_base->SPIP_DATA = tx_frame;
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}
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}
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}
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#endif
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static int transceive(const struct device *dev, const struct spi_config *spi_cfg,
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const struct spi_buf_set *tx_bufs, const struct spi_buf_set *rx_bufs,
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bool asynchronous, spi_callback_t cb, void *userdata)
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{
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const struct spi_npcx_spip_cfg *const config = dev->config;
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struct spip_reg *const reg_base = config->reg_base;
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struct spi_npcx_spip_data *const data = dev->data;
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struct spi_context *ctx = &data->ctx;
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int rc;
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if (!tx_bufs && !rx_bufs) {
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return 0;
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}
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#ifndef CONFIG_SPI_NPCX_SPIP_INTERRUPT
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if (asynchronous) {
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return -ENOTSUP;
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}
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#endif
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/* Lock the SPI Context */
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spi_context_lock(ctx, asynchronous, cb, userdata, spi_cfg);
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rc = spi_npcx_spip_configure(dev, spi_cfg);
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if (rc < 0) {
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spi_context_release(ctx, rc);
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return rc;
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}
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spi_context_buffers_setup(ctx, tx_bufs, rx_bufs, data->bytes_per_frame);
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if (!spi_npcx_spip_transfer_ongoing(data)) {
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spi_context_release(ctx, 0);
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return 0;
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}
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/* Enable SPIP module */
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reg_base->SPIP_CTL1 |= BIT(NPCX_SPIP_CTL1_SPIEN);
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/* Cleaning junk data in the buffer */
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while (IS_BIT_SET(reg_base->SPIP_STAT, NPCX_SPIP_STAT_RBF)) {
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uint8_t unused __attribute__((unused));
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unused = reg_base->SPIP_DATA;
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}
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/* Assert the CS line */
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spi_context_cs_control(ctx, true);
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#ifdef CONFIG_SPI_NPCX_SPIP_INTERRUPT
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reg_base->SPIP_CTL1 |= BIT(NPCX_SPIP_CTL1_EIR) | BIT(NPCX_SPIP_CTL1_EIW);
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rc = spi_context_wait_for_completion(&data->ctx);
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#else
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do {
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rc = spi_npcx_spip_xfer_frame(dev);
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if (rc < 0) {
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break;
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}
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} while (spi_npcx_spip_transfer_ongoing(data));
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/*
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* The CS might not de-assert if SPI_HOLD_ON_CS is configured.
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* In this case, CS de-assertion reles on the caller to explicitly call spi_release() API.
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*/
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spi_context_cs_control(ctx, false);
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#endif
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spi_context_release(ctx, rc);
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return rc;
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}
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static int spi_npcx_spip_transceive(const struct device *dev, const struct spi_config *spi_cfg,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs)
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{
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return transceive(dev, spi_cfg, tx_bufs, rx_bufs, false, NULL, NULL);
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}
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#ifdef CONFIG_SPI_ASYNC
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static int spi_npcx_spip_transceive_async(const struct device *dev,
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const struct spi_config *spi_cfg,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs, spi_callback_t cb,
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void *userdata)
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{
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return transceive(dev, spi_cfg, tx_bufs, rx_bufs, true, cb, userdata);
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}
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#endif
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static int spi_npcx_spip_release(const struct device *dev, const struct spi_config *spi_cfg)
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{
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struct spi_npcx_spip_data *const data = dev->data;
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struct spi_context *ctx = &data->ctx;
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if (!spi_context_configured(ctx, spi_cfg)) {
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return -EINVAL;
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}
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spi_context_unlock_unconditionally(ctx);
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return 0;
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}
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static int spi_npcx_spip_init(const struct device *dev)
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{
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int ret;
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struct spi_npcx_spip_data *const data = dev->data;
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const struct spi_npcx_spip_cfg *const config = dev->config;
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struct spip_reg *const reg_base = config->reg_base;
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const struct device *const clk_dev = DEVICE_DT_GET(NPCX_CLK_CTRL_NODE);
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if (!device_is_ready(clk_dev)) {
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LOG_ERR("clock control device not ready");
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return -ENODEV;
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}
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ret = clock_control_on(clk_dev, (clock_control_subsys_t)&config->clk_cfg);
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if (ret < 0) {
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LOG_ERR("Turn on SPIP clock fail %d", ret);
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return ret;
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}
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ret = clock_control_get_rate(clk_dev, (clock_control_subsys_t)&config->clk_cfg,
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&data->src_clock_freq);
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if (ret < 0) {
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LOG_ERR("Get SPIP clock source rate error %d", ret);
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return ret;
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}
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ret = spi_context_cs_configure_all(&data->ctx);
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if (ret < 0) {
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return ret;
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}
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ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
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if (ret < 0) {
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return ret;
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}
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/* Make sure the context is unlocked */
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spi_context_unlock_unconditionally(&data->ctx);
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#ifdef CONFIG_SPI_NPCX_SPIP_INTERRUPT
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config->irq_cfg_func(dev);
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#endif
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/* Enable SPIP module */
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reg_base->SPIP_CTL1 |= BIT(NPCX_SPIP_CTL1_SPIEN);
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return 0;
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}
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static struct spi_driver_api spi_npcx_spip_api = {
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.transceive = spi_npcx_spip_transceive,
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.release = spi_npcx_spip_release,
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#ifdef CONFIG_SPI_ASYNC
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.transceive_async = spi_npcx_spip_transceive_async,
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#endif
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#ifdef CONFIG_SPI_RTIO
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.iodev_submit = spi_rtio_iodev_default_submit,
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#endif
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};
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#ifdef CONFIG_SPI_NPCX_SPIP_INTERRUPT
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#define NPCX_SPIP_IRQ_HANDLER(n) \
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static void spi_npcx_spip_irq_cfg_func_##n(const struct device *dev) \
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{ \
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IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), spi_npcx_spip_isr, \
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DEVICE_DT_INST_GET(n), 0); \
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irq_enable(DT_INST_IRQN(n)); \
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}
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#define NPCX_SPIP_IRQ_HANDLER_FUNC(n) .irq_cfg_func = spi_npcx_spip_irq_cfg_func_##n,
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#else
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#define NPCX_SPIP_IRQ_HANDLER_FUNC(n)
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#define NPCX_SPIP_IRQ_HANDLER(n)
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#endif
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#define NPCX_SPI_INIT(n) \
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PINCTRL_DT_INST_DEFINE(n); \
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NPCX_SPIP_IRQ_HANDLER(n) \
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\
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static struct spi_npcx_spip_data spi_npcx_spip_data_##n = { \
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SPI_CONTEXT_INIT_LOCK(spi_npcx_spip_data_##n, ctx), \
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SPI_CONTEXT_INIT_SYNC(spi_npcx_spip_data_##n, ctx), \
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SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(n), ctx)}; \
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\
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static struct spi_npcx_spip_cfg spi_npcx_spip_cfg_##n = { \
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.reg_base = (struct spip_reg *)DT_INST_REG_ADDR(n), \
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.clk_cfg = NPCX_DT_CLK_CFG_ITEM(n), \
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
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NPCX_SPIP_IRQ_HANDLER_FUNC(n)}; \
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\
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DEVICE_DT_INST_DEFINE(n, spi_npcx_spip_init, NULL, &spi_npcx_spip_data_##n, \
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&spi_npcx_spip_cfg_##n, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, \
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&spi_npcx_spip_api);
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DT_INST_FOREACH_STATUS_OKAY(NPCX_SPI_INIT)
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