121 lines
3.3 KiB
C
121 lines
3.3 KiB
C
/*
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* Copyright (c) 2023 by Rivos Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/arch/cpu.h>
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#include <zephyr/drivers/uart.h>
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#include <zephyr/irq.h>
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/* Register offsets within the UART device register space. */
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#define UART_INTR_STATE_REG_OFFSET 0x0
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#define UART_INTR_ENABLE_REG_OFFSET 0x4
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#define UART_CTRL_REG_OFFSET 0x10
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#define UART_STATUS_REG_OFFSET 0x14
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#define UART_RDATA_REG_OFFSET 0x18
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#define UART_WDATA_REG_OFFSET 0x1c
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#define UART_FIFO_CTRL_REG_OFFSET 0x20
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#define UART_OVRD_REG_OFFSET 0x28
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#define UART_TIMEOUT_CTRL_REG_OFFSET 0x30
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/* Control register bits. */
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#define UART_CTRL_TX_BIT BIT(0)
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#define UART_CTRL_RX_BIT BIT(1)
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#define UART_CTRL_NCO_OFFSET 16
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/* FIFO control register bits. */
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#define UART_FIFO_CTRL_RXRST_BIT BIT(0)
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#define UART_FIFO_CTRL_TXRST_BIT BIT(1)
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/* Status register bits. */
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#define UART_STATUS_TXFULL_BIT BIT(0)
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#define UART_STATUS_RXEMPTY_BIT BIT(5)
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#define DT_DRV_COMPAT lowrisc_opentitan_uart
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struct uart_opentitan_config {
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mem_addr_t base;
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uint32_t nco_reg;
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};
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static int uart_opentitan_init(const struct device *dev)
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{
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const struct uart_opentitan_config *cfg = dev->config;
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/* Reset settings. */
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sys_write32(0u, cfg->base + UART_CTRL_REG_OFFSET);
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/* Clear FIFOs. */
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sys_write32(UART_FIFO_CTRL_RXRST_BIT | UART_FIFO_CTRL_TXRST_BIT,
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cfg->base + UART_FIFO_CTRL_REG_OFFSET);
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/* Clear other states. */
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sys_write32(0u, cfg->base + UART_OVRD_REG_OFFSET);
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sys_write32(0u, cfg->base + UART_TIMEOUT_CTRL_REG_OFFSET);
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/* Disable interrupts. */
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sys_write32(0u, cfg->base + UART_INTR_ENABLE_REG_OFFSET);
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/* Clear interrupts. */
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sys_write32(0xffffffffu, cfg->base + UART_INTR_STATE_REG_OFFSET);
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/* Set baud and enable TX and RX. */
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sys_write32(UART_CTRL_TX_BIT | UART_CTRL_RX_BIT |
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(cfg->nco_reg << UART_CTRL_NCO_OFFSET),
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cfg->base + UART_CTRL_REG_OFFSET);
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return 0;
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}
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static int uart_opentitan_poll_in(const struct device *dev, unsigned char *c)
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{
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const struct uart_opentitan_config *cfg = dev->config;
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if (sys_read32(cfg->base + UART_STATUS_REG_OFFSET) & UART_STATUS_RXEMPTY_BIT) {
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/* Empty RX FIFO */
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return -1;
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}
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*c = sys_read32(cfg->base + UART_RDATA_REG_OFFSET);
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return 0;
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}
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static void uart_opentitan_poll_out(const struct device *dev, unsigned char c)
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{
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const struct uart_opentitan_config *cfg = dev->config;
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/* Wait for space in the TX FIFO */
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while (sys_read32(cfg->base + UART_STATUS_REG_OFFSET) &
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UART_STATUS_TXFULL_BIT) {
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;
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}
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sys_write32(c, cfg->base + UART_WDATA_REG_OFFSET);
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}
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static const struct uart_driver_api uart_opentitan_driver_api = {
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.poll_in = uart_opentitan_poll_in,
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.poll_out = uart_opentitan_poll_out,
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};
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/* The baud rate is set by writing to the CTRL.NCO register, which is
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* calculated based on baud ticks per system clock tick multiplied by a
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* predefined scaler value.
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*/
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#define NCO_REG(baud, clk) (BIT64(20) * (baud) / (clk))
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#define UART_OPENTITAN_INIT(n) \
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static struct uart_opentitan_config uart_opentitan_config_##n = \
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{ \
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.base = DT_INST_REG_ADDR(n), \
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.nco_reg = NCO_REG(DT_INST_PROP(n, current_speed), \
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DT_INST_PROP(n, clock_frequency)), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(n, uart_opentitan_init, NULL, NULL, \
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&uart_opentitan_config_##n, \
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PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, \
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&uart_opentitan_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(UART_OPENTITAN_INIT)
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