333 lines
9.8 KiB
C
333 lines
9.8 KiB
C
/*
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* Copyright (c) 2023 honglin leng <a909204013@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT brcm_bcm2711_aux_uart
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/**
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* @brief BCM2711 Miniuart Serial Driver
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*
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/arch/cpu.h>
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#include <stdbool.h>
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#include <zephyr/sys/__assert.h>
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#include <zephyr/init.h>
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#include <zephyr/drivers/uart.h>
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#include <zephyr/irq.h>
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#define BCM2711_MU_IO 0x00
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#define BCM2711_MU_IER 0x04
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#define BCM2711_MU_IIR 0x08
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#define BCM2711_MU_LCR 0x0c
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#define BCM2711_MU_MCR 0x10
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#define BCM2711_MU_LSR 0x14
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#define BCM2711_MU_MSR 0x18
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#define BCM2711_MU_SCRATCH 0x1c
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#define BCM2711_MU_CNTL 0x20
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#define BCM2711_MU_STAT 0x24
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#define BCM2711_MU_BAUD 0x28
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#define BCM2711_MU_IER_TX_INTERRUPT BIT(1)
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#define BCM2711_MU_IER_RX_INTERRUPT BIT(0)
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#define BCM2711_MU_IIR_RX_INTERRUPT BIT(2)
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#define BCM2711_MU_IIR_TX_INTERRUPT BIT(1)
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#define BCM2711_MU_IIR_FLUSH 0xc6
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#define BCM2711_MU_LCR_7BIT 0x02
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#define BCM2711_MU_LCR_8BIT 0x03
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#define BCM2711_MU_LSR_TX_IDLE BIT(6)
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#define BCM2711_MU_LSR_TX_EMPTY BIT(5)
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#define BCM2711_MU_LSR_RX_OVERRUN BIT(1)
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#define BCM2711_MU_LSR_RX_READY BIT(0)
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#define BCM2711_MU_CNTL_RX_ENABLE BIT(0)
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#define BCM2711_MU_CNTL_TX_ENABLE BIT(1)
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struct bcm2711_uart_config {
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DEVICE_MMIO_ROM; /* Must be first */
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uint32_t baud_rate;
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uint32_t clocks;
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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void (*irq_config_func)(const struct device *dev);
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#endif
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};
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struct bcm2711_uart_data {
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DEVICE_MMIO_RAM; /* Must be first */
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mem_addr_t uart_addr;
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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uart_irq_callback_user_data_t callback;
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void *cb_data;
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#endif
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};
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static bool bcm2711_mu_lowlevel_can_getc(mem_addr_t base)
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{
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return sys_read32(base + BCM2711_MU_LSR) & BCM2711_MU_LSR_RX_READY;
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}
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static bool bcm2711_mu_lowlevel_can_putc(mem_addr_t base)
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{
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return sys_read32(base + BCM2711_MU_LSR) & BCM2711_MU_LSR_TX_EMPTY;
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}
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static void bcm2711_mu_lowlevel_putc(mem_addr_t base, uint8_t ch)
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{
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/* Wait until there is data in the FIFO */
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while (!bcm2711_mu_lowlevel_can_putc(base)) {
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;
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}
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/* Send the character */
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sys_write32(ch, base + BCM2711_MU_IO);
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}
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static void bcm2711_mu_lowlevel_init(mem_addr_t base, bool skip_baudrate_config,
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uint32_t baudrate, uint32_t input_clock)
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{
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uint32_t divider;
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/* Wait until there is data in the FIFO */
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while (!bcm2711_mu_lowlevel_can_putc(base)) {
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;
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}
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/* Disable port */
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sys_write32(0x0, base + BCM2711_MU_CNTL);
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/* Disable interrupts */
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sys_write32(0x0, base + BCM2711_MU_IER);
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/* Setup 8bit data width and baudrate */
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sys_write32(BCM2711_MU_LCR_8BIT, base + BCM2711_MU_LCR);
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if (!skip_baudrate_config) {
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divider = (input_clock / (baudrate * 8));
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sys_write32(divider - 1, base + BCM2711_MU_BAUD);
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}
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/* Enable RX & TX port */
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sys_write32(BCM2711_MU_CNTL_RX_ENABLE | BCM2711_MU_CNTL_TX_ENABLE, base + BCM2711_MU_CNTL);
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}
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/**
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* @brief Initialize UART channel
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*
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* This routine is called to reset the chip in a quiescent state.
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* It is assumed that this function is called only once per UART.
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*
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* @param dev UART device struct
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*
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* @return 0
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*/
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static int uart_bcm2711_init(const struct device *dev)
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{
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const struct bcm2711_uart_config *uart_cfg = dev->config;
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struct bcm2711_uart_data *uart_data = dev->data;
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DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);
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uart_data->uart_addr = DEVICE_MMIO_GET(dev);
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bcm2711_mu_lowlevel_init(uart_data->uart_addr, 1, uart_cfg->baud_rate, uart_cfg->clocks);
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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uart_cfg->irq_config_func(dev);
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#endif
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return 0;
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}
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static void uart_bcm2711_poll_out(const struct device *dev, unsigned char c)
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{
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struct bcm2711_uart_data *uart_data = dev->data;
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bcm2711_mu_lowlevel_putc(uart_data->uart_addr, c);
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}
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static int uart_bcm2711_poll_in(const struct device *dev, unsigned char *c)
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{
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struct bcm2711_uart_data *uart_data = dev->data;
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while (!bcm2711_mu_lowlevel_can_getc(uart_data->uart_addr)) {
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;
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}
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return sys_read32(uart_data->uart_addr + BCM2711_MU_IO) & 0xFF;
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}
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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static int uart_bcm2711_fifo_fill(const struct device *dev,
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const uint8_t *tx_data,
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int size)
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{
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int num_tx = 0U;
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struct bcm2711_uart_data *uart_data = dev->data;
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while ((size - num_tx) > 0) {
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/* Send a character */
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bcm2711_mu_lowlevel_putc(uart_data->uart_addr, tx_data[num_tx]);
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num_tx++;
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}
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return num_tx;
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}
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static int uart_bcm2711_fifo_read(const struct device *dev, uint8_t *rx_data,
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const int size)
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{
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int num_rx = 0U;
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struct bcm2711_uart_data *uart_data = dev->data;
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while ((size - num_rx) > 0 && bcm2711_mu_lowlevel_can_getc(uart_data->uart_addr)) {
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/* Receive a character */
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rx_data[num_rx++] = sys_read32(uart_data->uart_addr + BCM2711_MU_IO) & 0xFF;
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}
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return num_rx;
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}
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static void uart_bcm2711_irq_tx_enable(const struct device *dev)
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{
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struct bcm2711_uart_data *uart_data = dev->data;
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sys_write32(BCM2711_MU_IER_TX_INTERRUPT, uart_data->uart_addr + BCM2711_MU_IER);
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}
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static void uart_bcm2711_irq_tx_disable(const struct device *dev)
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{
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struct bcm2711_uart_data *uart_data = dev->data;
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sys_write32((uint32_t)(~BCM2711_MU_IER_TX_INTERRUPT),
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uart_data->uart_addr + BCM2711_MU_IER);
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}
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static int uart_bcm2711_irq_tx_ready(const struct device *dev)
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{
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struct bcm2711_uart_data *uart_data = dev->data;
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return bcm2711_mu_lowlevel_can_putc(uart_data->uart_addr);
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}
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static void uart_bcm2711_irq_rx_enable(const struct device *dev)
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{
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struct bcm2711_uart_data *uart_data = dev->data;
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sys_write32(BCM2711_MU_IER_RX_INTERRUPT, uart_data->uart_addr + BCM2711_MU_IER);
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}
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static void uart_bcm2711_irq_rx_disable(const struct device *dev)
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{
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struct bcm2711_uart_data *uart_data = dev->data;
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sys_write32((uint32_t)(~BCM2711_MU_IER_RX_INTERRUPT),
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uart_data->uart_addr + BCM2711_MU_IER);
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}
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static int uart_bcm2711_irq_rx_ready(const struct device *dev)
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{
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struct bcm2711_uart_data *uart_data = dev->data;
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return bcm2711_mu_lowlevel_can_getc(uart_data->uart_addr);
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}
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static int uart_bcm2711_irq_is_pending(const struct device *dev)
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{
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struct bcm2711_uart_data *uart_data = dev->data;
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return bcm2711_mu_lowlevel_can_getc(uart_data->uart_addr) ||
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bcm2711_mu_lowlevel_can_putc(uart_data->uart_addr);
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}
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static int uart_bcm2711_irq_update(const struct device *dev)
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{
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return 1;
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}
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static void uart_bcm2711_irq_callback_set(const struct device *dev,
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uart_irq_callback_user_data_t cb,
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void *cb_data)
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{
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struct bcm2711_uart_data *data = dev->data;
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data->callback = cb;
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data->cb_data = cb_data;
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}
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/**
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* @brief Interrupt service routine.
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*
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* This simply calls the callback function, if one exists.
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*
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* Note: imx UART Tx interrupts when ready to send; Rx interrupts when char
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* received.
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*
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* @param arg Argument to ISR.
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*/
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void uart_isr(const struct device *dev)
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{
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struct bcm2711_uart_data *data = dev->data;
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if (data->callback) {
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data->callback(dev, data->cb_data);
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}
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}
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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static const struct uart_driver_api uart_bcm2711_driver_api = {
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.poll_in = uart_bcm2711_poll_in,
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.poll_out = uart_bcm2711_poll_out,
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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.fifo_fill = uart_bcm2711_fifo_fill,
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.fifo_read = uart_bcm2711_fifo_read,
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.irq_tx_enable = uart_bcm2711_irq_tx_enable,
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.irq_tx_disable = uart_bcm2711_irq_tx_disable,
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.irq_tx_ready = uart_bcm2711_irq_tx_ready,
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.irq_rx_enable = uart_bcm2711_irq_rx_enable,
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.irq_rx_disable = uart_bcm2711_irq_rx_disable,
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.irq_rx_ready = uart_bcm2711_irq_rx_ready,
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.irq_is_pending = uart_bcm2711_irq_is_pending,
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.irq_update = uart_bcm2711_irq_update,
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.irq_callback_set = uart_bcm2711_irq_callback_set,
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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};
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#define UART_DECLARE_CFG(n, IRQ_FUNC_INIT) \
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static const struct bcm2711_uart_config bcm2711_uart_##n##_config = { \
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DEVICE_MMIO_ROM_INIT(DT_DRV_INST(n)), .baud_rate = DT_INST_PROP(n, current_speed), \
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.clocks = DT_INST_PROP(n, clock_frequency), IRQ_FUNC_INIT}
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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#define UART_CONFIG_FUNC(n) \
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static void irq_config_func_##n(const struct device *dev) \
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{ \
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IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), uart_isr, \
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DEVICE_DT_INST_GET(n), 0); \
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irq_enable(DT_INST_IRQN(n)); \
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}
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#define UART_IRQ_CFG_FUNC_INIT(n) .irq_config_func = irq_config_func_##n
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#define UART_INIT_CFG(n) UART_DECLARE_CFG(n, UART_IRQ_CFG_FUNC_INIT(n))
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#else
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#define UART_CONFIG_FUNC(n)
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#define UART_IRQ_CFG_FUNC_INIT
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#define UART_INIT_CFG(n) UART_DECLARE_CFG(n, UART_IRQ_CFG_FUNC_INIT)
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#endif
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#define UART_INIT(n) \
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static struct bcm2711_uart_data bcm2711_uart_##n##_data; \
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\
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static const struct bcm2711_uart_config bcm2711_uart_##n##_config; \
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\
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DEVICE_DT_INST_DEFINE(n, &uart_bcm2711_init, NULL, &bcm2711_uart_##n##_data, \
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&bcm2711_uart_##n##_config, PRE_KERNEL_1, \
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CONFIG_SERIAL_INIT_PRIORITY, &uart_bcm2711_driver_api); \
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\
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UART_CONFIG_FUNC(n) \
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\
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UART_INIT_CFG(n);
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DT_INST_FOREACH_STATUS_OKAY(UART_INIT)
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