277 lines
9.3 KiB
C
277 lines
9.3 KiB
C
/*
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* (c) Meta Platforms, Inc. and affiliates.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_ctimer_pwm
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#include <errno.h>
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#include <fsl_ctimer.h>
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#include <fsl_clock.h>
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#include <zephyr/drivers/pwm.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(pwm_mcux_ctimer, CONFIG_PWM_LOG_LEVEL);
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#define CHANNEL_COUNT kCTIMER_Match_3 + 1
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enum pwm_ctimer_channel_role {
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PWM_CTIMER_CHANNEL_ROLE_NONE = 0,
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PWM_CTIMER_CHANNEL_ROLE_PULSE,
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PWM_CTIMER_CHANNEL_ROLE_PERIOD,
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};
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struct pwm_ctimer_channel_state {
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enum pwm_ctimer_channel_role role;
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uint32_t cycles;
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};
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struct pwm_mcux_ctimer_data {
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struct pwm_ctimer_channel_state channel_states[CHANNEL_COUNT];
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ctimer_match_t current_period_channel;
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bool is_period_channel_set;
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uint32_t num_active_pulse_chans;
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};
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struct pwm_mcux_ctimer_config {
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CTIMER_Type *base;
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uint32_t prescale;
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uint32_t period_channel;
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const struct device *clock_control;
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clock_control_subsys_t clock_id;
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const struct pinctrl_dev_config *pincfg;
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};
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/*
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* All pwm signals generated from the same ctimer must have same period. To avoid this, we check
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* if the new parameters will NOT change the period for a ctimer with active pulse channels
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*/
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static bool mcux_ctimer_pwm_is_period_valid(struct pwm_mcux_ctimer_data *data,
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uint32_t new_pulse_channel, uint32_t new_period_cycles,
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uint32_t current_period_channel)
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{
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/* if we aren't changing the period, we're ok */
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if (data->channel_states[current_period_channel].cycles == new_period_cycles) {
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return true;
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}
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/*
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* if we are changing it but there aren't any pulse channels that depend on it, then we're
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* ok too
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*/
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if (data->num_active_pulse_chans == 0) {
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return true;
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}
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if (data->num_active_pulse_chans > 1) {
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return false;
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}
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/*
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* there is exactly one pulse channel that depends on existing period and its not the
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* one we're changing now
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*/
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if (data->channel_states[new_pulse_channel].role != PWM_CTIMER_CHANNEL_ROLE_PULSE) {
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return false;
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}
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return true;
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}
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/*
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* Each ctimer channel can either be used as a pulse or period channel. Each channel has a counter.
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* The duty cycle is counted by the pulse channel. When the period channel counts down, it resets
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* the pulse channel (and all counters in the ctimer instance). The pwm api does not permit us to
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* specify a period channel (only pulse channel). So we need to figure out an acceptable period
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* channel in the driver (if that's even possible)
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*/
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static int mcux_ctimer_pwm_select_period_channel(struct pwm_mcux_ctimer_data *data,
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uint32_t new_pulse_channel,
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uint32_t new_period_cycles,
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uint32_t *ret_period_channel)
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{
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if (data->is_period_channel_set) {
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if (!mcux_ctimer_pwm_is_period_valid(data, new_pulse_channel, new_period_cycles,
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data->current_period_channel)) {
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LOG_ERR("Cannot set channel %u to %u as period channel",
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*ret_period_channel, new_period_cycles);
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return -EINVAL;
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}
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*ret_period_channel = data->current_period_channel;
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if (new_pulse_channel != *ret_period_channel) {
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/* the existing period channel will not conflict with new pulse_channel */
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return 0;
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}
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}
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/* we need to find an unused channel to use as period_channel */
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*ret_period_channel = new_pulse_channel + 1;
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*ret_period_channel %= CHANNEL_COUNT;
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while (data->channel_states[*ret_period_channel].role != PWM_CTIMER_CHANNEL_ROLE_NONE) {
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if (new_pulse_channel == *ret_period_channel) {
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LOG_ERR("no available channel for period counter");
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return -EBUSY;
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}
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(*ret_period_channel)++;
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*ret_period_channel %= CHANNEL_COUNT;
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}
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return 0;
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}
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static void mcux_ctimer_pwm_update_state(struct pwm_mcux_ctimer_data *data, uint32_t pulse_channel,
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uint32_t pulse_cycles, uint32_t period_channel,
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uint32_t period_cycles)
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{
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if (data->channel_states[pulse_channel].role != PWM_CTIMER_CHANNEL_ROLE_PULSE) {
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data->num_active_pulse_chans++;
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}
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data->channel_states[pulse_channel].role = PWM_CTIMER_CHANNEL_ROLE_PULSE;
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data->channel_states[pulse_channel].cycles = pulse_cycles;
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data->is_period_channel_set = true;
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data->current_period_channel = period_channel;
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data->channel_states[period_channel].role = PWM_CTIMER_CHANNEL_ROLE_PERIOD;
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data->channel_states[period_channel].cycles = period_cycles;
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}
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static int mcux_ctimer_pwm_set_cycles(const struct device *dev, uint32_t pulse_channel,
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uint32_t period_cycles, uint32_t pulse_cycles,
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pwm_flags_t flags)
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{
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const struct pwm_mcux_ctimer_config *config = dev->config;
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struct pwm_mcux_ctimer_data *data = dev->data;
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uint32_t period_channel = data->current_period_channel;
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int ret = 0;
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status_t status;
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if (pulse_channel >= CHANNEL_COUNT) {
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LOG_ERR("Invalid channel %u. muse be less than %u", pulse_channel, CHANNEL_COUNT);
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return -EINVAL;
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}
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if (period_cycles == 0) {
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LOG_ERR("Channel can not be set to zero");
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return -ENOTSUP;
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}
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ret = mcux_ctimer_pwm_select_period_channel(data, pulse_channel, period_cycles,
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&period_channel);
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if (ret != 0) {
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LOG_ERR("could not select valid period channel. ret=%d", ret);
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return ret;
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}
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if (flags & PWM_POLARITY_INVERTED) {
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if (pulse_cycles == 0) {
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/* make pulse cycles greater than period so event never occurs */
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pulse_cycles = period_cycles + 1;
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} else {
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pulse_cycles = period_cycles - pulse_cycles;
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}
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}
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status = CTIMER_SetupPwmPeriod(config->base, period_channel, pulse_channel, period_cycles,
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pulse_cycles, false);
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if (kStatus_Success != status) {
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LOG_ERR("failed setup pwm period. status=%d", status);
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return -EIO;
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}
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mcux_ctimer_pwm_update_state(data, pulse_channel, pulse_cycles, period_channel,
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period_cycles);
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CTIMER_StartTimer(config->base);
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return 0;
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}
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static int mcux_ctimer_pwm_get_cycles_per_sec(const struct device *dev, uint32_t channel,
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uint64_t *cycles)
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{
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const struct pwm_mcux_ctimer_config *config = dev->config;
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int err = 0;
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/* clean up upper word of return parameter */
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*cycles &= 0xFFFFFFFF;
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err = clock_control_get_rate(config->clock_control, config->clock_id, (uint32_t *)cycles);
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if (err != 0) {
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LOG_ERR("could not get clock rate");
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return err;
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}
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if (config->prescale > 0) {
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*cycles /= config->prescale;
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}
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return err;
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}
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static int mcux_ctimer_pwm_init(const struct device *dev)
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{
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const struct pwm_mcux_ctimer_config *config = dev->config;
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ctimer_config_t pwm_config;
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int err;
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err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
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if (err) {
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return err;
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}
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if (config->period_channel >= CHANNEL_COUNT) {
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LOG_ERR("invalid period_channel: %d. must be less than %d", config->period_channel,
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CHANNEL_COUNT);
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return -EINVAL;
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}
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CTIMER_GetDefaultConfig(&pwm_config);
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pwm_config.prescale = config->prescale;
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CTIMER_Init(config->base, &pwm_config);
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return 0;
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}
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static const struct pwm_driver_api pwm_mcux_ctimer_driver_api = {
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.set_cycles = mcux_ctimer_pwm_set_cycles,
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.get_cycles_per_sec = mcux_ctimer_pwm_get_cycles_per_sec,
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};
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#define PWM_MCUX_CTIMER_PINCTRL_DEFINE(n) PINCTRL_DT_INST_DEFINE(n);
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#define PWM_MCUX_CTIMER_PINCTRL_INIT(n) .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),
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#define PWM_MCUX_CTIMER_DEVICE_INIT_MCUX(n) \
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static struct pwm_mcux_ctimer_data pwm_mcux_ctimer_data_##n = { \
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.channel_states = \
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{ \
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[kCTIMER_Match_0] = {.role = PWM_CTIMER_CHANNEL_ROLE_NONE, \
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.cycles = 0}, \
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[kCTIMER_Match_1] = {.role = PWM_CTIMER_CHANNEL_ROLE_NONE, \
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.cycles = 0}, \
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[kCTIMER_Match_2] = {.role = PWM_CTIMER_CHANNEL_ROLE_NONE, \
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.cycles = 0}, \
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[kCTIMER_Match_3] = {.role = PWM_CTIMER_CHANNEL_ROLE_NONE, \
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.cycles = 0}, \
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}, \
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.current_period_channel = kCTIMER_Match_0, \
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.is_period_channel_set = false, \
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}; \
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PWM_MCUX_CTIMER_PINCTRL_DEFINE(n) \
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static const struct pwm_mcux_ctimer_config pwm_mcux_ctimer_config_##n = { \
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.base = (CTIMER_Type *)DT_INST_REG_ADDR(n), \
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.prescale = DT_INST_PROP(n, prescaler), \
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.clock_control = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
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.clock_id = (clock_control_subsys_t)(DT_INST_CLOCKS_CELL(n, name)), \
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PWM_MCUX_CTIMER_PINCTRL_INIT(n)}; \
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\
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DEVICE_DT_INST_DEFINE(n, mcux_ctimer_pwm_init, NULL, &pwm_mcux_ctimer_data_##n, \
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&pwm_mcux_ctimer_config_##n, POST_KERNEL, \
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &pwm_mcux_ctimer_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(PWM_MCUX_CTIMER_DEVICE_INIT_MCUX)
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