273 lines
7.4 KiB
C
273 lines
7.4 KiB
C
/*
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* Copyright (c) 2019, Linaro
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_imx_pwm
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#include <errno.h>
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#include <zephyr/drivers/pwm.h>
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#include <zephyr/drivers/clock_control.h>
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#include <soc.h>
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#include <fsl_pwm.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/kernel.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(pwm_mcux, CONFIG_PWM_LOG_LEVEL);
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#define CHANNEL_COUNT 2
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struct pwm_mcux_config {
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PWM_Type *base;
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uint8_t index;
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const struct device *clock_dev;
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clock_control_subsys_t clock_subsys;
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pwm_clock_prescale_t prescale;
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pwm_register_reload_t reload;
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pwm_mode_t mode;
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bool run_wait;
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bool run_debug;
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const struct pinctrl_dev_config *pincfg;
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};
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struct pwm_mcux_data {
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uint32_t period_cycles[CHANNEL_COUNT];
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pwm_signal_param_t channel[CHANNEL_COUNT];
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struct k_mutex lock;
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};
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static int mcux_pwm_set_cycles_internal(const struct device *dev, uint32_t channel,
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uint32_t period_cycles, uint32_t pulse_cycles,
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pwm_flags_t flags)
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{
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const struct pwm_mcux_config *config = dev->config;
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struct pwm_mcux_data *data = dev->data;
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pwm_level_select_t level;
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if (flags & PWM_POLARITY_INVERTED) {
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level = kPWM_LowTrue;
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} else {
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level = kPWM_HighTrue;
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}
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if (period_cycles != data->period_cycles[channel]
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|| level != data->channel[channel].level) {
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uint32_t clock_freq;
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status_t status;
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data->period_cycles[channel] = period_cycles;
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if (clock_control_get_rate(config->clock_dev, config->clock_subsys,
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&clock_freq)) {
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return -EINVAL;
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}
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data->channel[channel].pwmchannelenable = true;
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PWM_StopTimer(config->base, 1U << config->index);
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/*
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* We will directly write the duty cycle pulse width
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* and full pulse width into the VALx registers to
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* setup PWM with higher resolution.
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* Therefore we use dummy values for the duty cycle
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* and frequency.
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*/
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data->channel[channel].dutyCyclePercent = 0;
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data->channel[channel].level = level;
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status = PWM_SetupPwm(config->base, config->index,
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&data->channel[channel], 1U,
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config->mode, 1U, clock_freq);
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if (status != kStatus_Success) {
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LOG_ERR("Could not set up pwm");
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return -ENOTSUP;
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}
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/* Setup VALx values directly for edge aligned PWM */
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if (channel == 0) {
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/* Side A */
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PWM_SetVALxValue(config->base, config->index,
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kPWM_ValueRegister_0,
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(uint16_t)(period_cycles / 2U));
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PWM_SetVALxValue(config->base, config->index,
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kPWM_ValueRegister_1,
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(uint16_t)(period_cycles - 1U));
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PWM_SetVALxValue(config->base, config->index,
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kPWM_ValueRegister_2, 0U);
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PWM_SetVALxValue(config->base, config->index,
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kPWM_ValueRegister_3,
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(uint16_t)pulse_cycles);
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} else {
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/* Side B */
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PWM_SetVALxValue(config->base, config->index,
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kPWM_ValueRegister_0,
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(uint16_t)(period_cycles / 2U));
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PWM_SetVALxValue(config->base, config->index,
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kPWM_ValueRegister_1,
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(uint16_t)(period_cycles - 1U));
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PWM_SetVALxValue(config->base, config->index,
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kPWM_ValueRegister_4, 0U);
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PWM_SetVALxValue(config->base, config->index,
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kPWM_ValueRegister_5,
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(uint16_t)pulse_cycles);
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}
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PWM_SetPwmLdok(config->base, 1U << config->index, true);
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PWM_StartTimer(config->base, 1U << config->index);
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} else {
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/* Setup VALx values directly for edge aligned PWM */
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if (channel == 0) {
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/* Side A */
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PWM_SetVALxValue(config->base, config->index,
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kPWM_ValueRegister_2, 0U);
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PWM_SetVALxValue(config->base, config->index,
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kPWM_ValueRegister_3,
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(uint16_t)pulse_cycles);
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} else {
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/* Side B */
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PWM_SetVALxValue(config->base, config->index,
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kPWM_ValueRegister_4, 0U);
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PWM_SetVALxValue(config->base, config->index,
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kPWM_ValueRegister_5,
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(uint16_t)pulse_cycles);
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}
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PWM_SetPwmLdok(config->base, 1U << config->index, true);
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}
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return 0;
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}
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static int mcux_pwm_set_cycles(const struct device *dev, uint32_t channel,
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uint32_t period_cycles, uint32_t pulse_cycles,
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pwm_flags_t flags)
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{
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struct pwm_mcux_data *data = dev->data;
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int result;
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if (channel >= CHANNEL_COUNT) {
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LOG_ERR("Invalid channel");
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return -EINVAL;
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}
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if (period_cycles == 0) {
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LOG_ERR("Channel can not be set to inactive level");
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return -ENOTSUP;
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}
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if (period_cycles > UINT16_MAX) {
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/* 16-bit resolution */
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LOG_ERR("Too long period (%u), adjust pwm prescaler!",
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period_cycles);
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/* TODO: dynamically adjust prescaler */
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return -EINVAL;
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}
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k_mutex_lock(&data->lock, K_FOREVER);
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result = mcux_pwm_set_cycles_internal(dev, channel, period_cycles, pulse_cycles, flags);
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k_mutex_unlock(&data->lock);
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return result;
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}
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static int mcux_pwm_get_cycles_per_sec(const struct device *dev,
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uint32_t channel, uint64_t *cycles)
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{
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const struct pwm_mcux_config *config = dev->config;
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uint32_t clock_freq;
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if (clock_control_get_rate(config->clock_dev, config->clock_subsys,
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&clock_freq)) {
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return -EINVAL;
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}
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*cycles = clock_freq >> config->prescale;
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return 0;
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}
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static int pwm_mcux_init(const struct device *dev)
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{
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const struct pwm_mcux_config *config = dev->config;
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struct pwm_mcux_data *data = dev->data;
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pwm_config_t pwm_config;
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status_t status;
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int i, err;
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k_mutex_init(&data->lock);
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if (!device_is_ready(config->clock_dev)) {
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LOG_ERR("clock control device not ready");
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return -ENODEV;
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}
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err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
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if (err < 0) {
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return err;
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}
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LOG_DBG("Set prescaler %d, reload mode %d",
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1 << config->prescale, config->reload);
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PWM_GetDefaultConfig(&pwm_config);
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pwm_config.prescale = config->prescale;
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pwm_config.reloadLogic = config->reload;
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pwm_config.clockSource = kPWM_BusClock;
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pwm_config.enableDebugMode = config->run_debug;
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#if !defined(FSL_FEATURE_PWM_HAS_NO_WAITEN) || (!FSL_FEATURE_PWM_HAS_NO_WAITEN)
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pwm_config.enableWait = config->run_wait;
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#endif
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status = PWM_Init(config->base, config->index, &pwm_config);
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if (status != kStatus_Success) {
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LOG_ERR("Unable to init PWM");
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return -EIO;
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}
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/* Disable fault sources */
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for (i = 0; i < FSL_FEATURE_PWM_FAULT_CH_COUNT; i++) {
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config->base->SM[config->index].DISMAP[i] = 0x0000;
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}
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data->channel[0].pwmChannel = kPWM_PwmA;
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data->channel[0].level = kPWM_HighTrue;
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data->channel[1].pwmChannel = kPWM_PwmB;
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data->channel[1].level = kPWM_HighTrue;
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return 0;
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}
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static const struct pwm_driver_api pwm_mcux_driver_api = {
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.set_cycles = mcux_pwm_set_cycles,
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.get_cycles_per_sec = mcux_pwm_get_cycles_per_sec,
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};
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#define PWM_DEVICE_INIT_MCUX(n) \
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static struct pwm_mcux_data pwm_mcux_data_ ## n; \
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PINCTRL_DT_INST_DEFINE(n); \
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\
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static const struct pwm_mcux_config pwm_mcux_config_ ## n = { \
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.base = (PWM_Type *)DT_REG_ADDR(DT_INST_PARENT(n)), \
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.index = DT_INST_PROP(n, index), \
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.mode = kPWM_EdgeAligned, \
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.prescale = _CONCAT(kPWM_Prescale_Divide_, DT_INST_PROP(n, nxp_prescaler)),\
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.reload = DT_ENUM_IDX_OR(DT_DRV_INST(n), nxp_reload,\
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kPWM_ReloadPwmFullCycle),\
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.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
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.clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name),\
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.run_wait = DT_INST_PROP(n, run_in_wait), \
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.run_debug = DT_INST_PROP(n, run_in_debug), \
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.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(n, \
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pwm_mcux_init, \
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NULL, \
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&pwm_mcux_data_ ## n, \
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&pwm_mcux_config_ ## n, \
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POST_KERNEL, CONFIG_PWM_INIT_PRIORITY, \
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&pwm_mcux_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(PWM_DEVICE_INIT_MCUX)
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