64 lines
1.9 KiB
C
64 lines
1.9 KiB
C
/*
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* Copyright 2022, 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/drivers/pinctrl.h>
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/* SIUL2 Multiplexed Signal Configuration Register */
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#define SIUL2_MSCR(n) (0x240 + 0x4 * (n))
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/* SIUL2 Input Multiplexed Signal Configuration Register */
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#define SIUL2_IMCR(n) (0xa40 + 0x4 * (n))
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#define SIUL2_MSCR_MAX_IDX 512U
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#define SIUL2_IMCR_MAX_IDX 512U
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/*
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* Utility macro that expands to the SIUL2 base address if it exists or zero.
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* Note that some devices may have instance gaps, hence the need to keep them in the array.
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*/
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#define SIUL2_BASE_OR_ZERO(nodelabel) \
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COND_CODE_1(DT_NODE_EXISTS(DT_NODELABEL(nodelabel)), \
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(DT_REG_ADDR(DT_NODELABEL(nodelabel))), (0U))
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static mem_addr_t siul2_bases[] = {
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SIUL2_BASE_OR_ZERO(siul2_0), SIUL2_BASE_OR_ZERO(siul2_1), SIUL2_BASE_OR_ZERO(siul2_2),
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SIUL2_BASE_OR_ZERO(siul2_3), SIUL2_BASE_OR_ZERO(siul2_4), SIUL2_BASE_OR_ZERO(siul2_5),
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};
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static void pinctrl_configure_pin(const pinctrl_soc_pin_t *pin)
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{
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mem_addr_t base;
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/* Multiplexed Signal Configuration */
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__ASSERT_NO_MSG(pin->mscr.inst < ARRAY_SIZE(siul2_bases));
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base = siul2_bases[pin->mscr.inst];
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__ASSERT_NO_MSG(base != 0);
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__ASSERT_NO_MSG(pin->mscr.idx < SIUL2_MSCR_MAX_IDX);
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sys_write32(pin->mscr.val, (base + SIUL2_MSCR(pin->mscr.idx)));
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/* Input Multiplexed Signal Configuration */
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if (pin->mscr.val & SIUL2_MSCR_IBE_MASK) {
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__ASSERT_NO_MSG(pin->imcr.inst < ARRAY_SIZE(siul2_bases));
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base = siul2_bases[pin->imcr.inst];
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__ASSERT_NO_MSG(base != 0);
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__ASSERT_NO_MSG(pin->imcr.idx < SIUL2_IMCR_MAX_IDX);
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sys_write32(pin->imcr.val, (base + SIUL2_IMCR(pin->imcr.idx)));
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}
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}
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
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{
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ARG_UNUSED(reg);
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for (uint8_t i = 0; i < pin_cnt; i++) {
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pinctrl_configure_pin(pins++);
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}
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return 0;
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}
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