66 lines
2.5 KiB
C
66 lines
2.5 KiB
C
/*
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* Copyright (c) 2024, Ambiq Micro Inc. <www.ambiq.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef MSPI_AMBIQ_H_
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#define MSPI_AMBIQ_H_
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#include <am_mcu_apollo.h>
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/* Hand-calculated minimum heap sizes needed to return a successful
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* 1-byte allocation. See details in lib/os/heap.[ch]
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*/
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#define MSPI_AMBIQ_HEAP_MIN_SIZE (sizeof(void *) > 4 ? 56 : 44)
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#define MSPI_AMBIQ_HEAP_DEFINE(name, bytes) \
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char __attribute__((section(".mspi_buff"))) \
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kheap_##name[MAX(bytes, MSPI_AMBIQ_HEAP_MIN_SIZE)]; \
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STRUCT_SECTION_ITERABLE(k_heap, name) = { \
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.heap = \
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{ \
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.init_mem = kheap_##name, \
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.init_bytes = MAX(bytes, MSPI_AMBIQ_HEAP_MIN_SIZE), \
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}, \
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}
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struct mspi_ambiq_timing_cfg {
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uint8_t ui8WriteLatency;
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uint8_t ui8TurnAround;
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bool bTxNeg;
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bool bRxNeg;
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bool bRxCap;
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uint32_t ui32TxDQSDelay;
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uint32_t ui32RxDQSDelay;
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uint32_t ui32RXDQSDelayEXT;
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};
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enum mspi_ambiq_timing_param {
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MSPI_AMBIQ_SET_WLC = BIT(0),
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MSPI_AMBIQ_SET_RLC = BIT(1),
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MSPI_AMBIQ_SET_TXNEG = BIT(2),
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MSPI_AMBIQ_SET_RXNEG = BIT(3),
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MSPI_AMBIQ_SET_RXCAP = BIT(4),
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MSPI_AMBIQ_SET_TXDQSDLY = BIT(5),
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MSPI_AMBIQ_SET_RXDQSDLY = BIT(6),
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MSPI_AMBIQ_SET_RXDQSDLYEXT = BIT(7),
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};
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#define MSPI_PORT(n) ((DT_REG_ADDR(DT_INST_BUS(n)) - MSPI0_BASE) / \
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(DT_REG_SIZE(DT_INST_BUS(n)) * 4))
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#define TIMING_CFG_GET_RX_DUMMY(cfg) \
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{ \
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mspi_timing_cfg *timing = (mspi_timing_cfg *)cfg; \
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timing->ui8TurnAround; \
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}
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#define TIMING_CFG_SET_RX_DUMMY(cfg, num) \
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{ \
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mspi_timing_cfg *timing = (mspi_timing_cfg *)cfg; \
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timing->ui8TurnAround = num; \
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}
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#endif
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