461 lines
17 KiB
C
461 lines
17 KiB
C
/*
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* Copyright (c) 2024, Ambiq Micro Inc. <www.ambiq.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT mspi_aps6404l
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#include <zephyr/kernel.h>
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#include <zephyr/pm/device.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/mspi.h>
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#if CONFIG_SOC_FAMILY_AMBIQ
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#include "mspi_ambiq.h"
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typedef struct mspi_ambiq_timing_cfg mspi_timing_cfg;
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typedef enum mspi_ambiq_timing_param mspi_timing_param;
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#else
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typedef struct mspi_timing_cfg mspi_timing_cfg;
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typedef enum mspi_timing_param mspi_timing_param;
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#endif
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LOG_MODULE_REGISTER(memc_mspi_aps6404l, CONFIG_MEMC_LOG_LEVEL);
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#define APM_VENDOR_ID 0xD
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#define APS6404L_WRITE 0x02
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#define APS6404L_READ 0x03
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#define APS6404L_FAST_READ 0x0B
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#define APS6404L_QUAD_MODE_ENTER 0x35
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#define APS6404L_QUAD_WRITE 0x38
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#define APS6404L_RESET_ENABLE 0x66
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#define APS6404L_RESET_MEMORY 0x99
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#define APS6404L_READ_ID 0x9F
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#define APS6404L_HALF_SLEEP_ENTER 0xC0
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#define APS6404L_QUAD_READ 0xEB
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#define APS6404L_QUAD_MODE_EXIT 0xF5
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struct memc_mspi_aps6404l_config {
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uint32_t port;
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uint32_t mem_size;
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const struct device *bus;
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struct mspi_dev_id dev_id;
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struct mspi_dev_cfg serial_cfg;
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struct mspi_dev_cfg quad_cfg;
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struct mspi_dev_cfg tar_dev_cfg;
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struct mspi_xip_cfg tar_xip_cfg;
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struct mspi_scramble_cfg tar_scramble_cfg;
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mspi_timing_cfg tar_timing_cfg;
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mspi_timing_param timing_cfg_mask;
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bool sw_multi_periph;
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};
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struct memc_mspi_aps6404l_data {
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struct mspi_dev_cfg dev_cfg;
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struct mspi_xip_cfg xip_cfg;
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struct mspi_scramble_cfg scramble_cfg;
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mspi_timing_cfg timing_cfg;
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struct mspi_xfer trans;
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struct mspi_xfer_packet packet;
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struct k_sem lock;
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};
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static int memc_mspi_aps6404l_command_write(const struct device *psram, uint8_t cmd, uint32_t addr,
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uint8_t *wdata, uint32_t length)
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{
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const struct memc_mspi_aps6404l_config *cfg = psram->config;
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struct memc_mspi_aps6404l_data *data = psram->data;
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int ret;
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uint8_t buffer[16];
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data->packet.dir = MSPI_TX;
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data->packet.cmd = cmd;
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data->packet.address = addr;
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data->packet.data_buf = buffer;
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data->packet.num_bytes = length;
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data->trans.async = false;
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data->trans.xfer_mode = MSPI_PIO;
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data->trans.tx_dummy = 0;
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data->trans.cmd_length = 1;
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data->trans.addr_length = 0;
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data->trans.hold_ce = false;
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data->trans.packets = &data->packet;
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data->trans.num_packet = 1;
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data->trans.timeout = 10;
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if (wdata != NULL) {
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memcpy(buffer, wdata, length);
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}
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ret = mspi_transceive(cfg->bus, &cfg->dev_id, (const struct mspi_xfer *)&data->trans);
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if (ret) {
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LOG_ERR("MSPI write transaction failed with code: %d/%u", ret, __LINE__);
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return -EIO;
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}
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return ret;
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}
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static int memc_mspi_aps6404l_command_read(const struct device *psram, uint8_t cmd, uint32_t addr,
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uint8_t *rdata, uint32_t length)
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{
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const struct memc_mspi_aps6404l_config *cfg = psram->config;
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struct memc_mspi_aps6404l_data *data = psram->data;
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int ret;
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uint8_t buffer[16];
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data->packet.dir = MSPI_RX;
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data->packet.cmd = cmd;
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data->packet.address = addr;
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data->packet.data_buf = buffer;
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data->packet.num_bytes = length;
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data->trans.async = false;
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data->trans.xfer_mode = MSPI_PIO;
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data->trans.rx_dummy = 0;
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data->trans.cmd_length = 1;
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data->trans.addr_length = 3;
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data->trans.hold_ce = false;
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data->trans.packets = &data->packet;
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data->trans.num_packet = 1;
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data->trans.timeout = 10;
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ret = mspi_transceive(cfg->bus, &cfg->dev_id, (const struct mspi_xfer *)&data->trans);
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if (ret) {
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LOG_ERR("MSPI read transaction failed with code: %d/%u", ret, __LINE__);
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return -EIO;
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}
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memcpy(rdata, buffer, length);
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return ret;
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}
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static void acquire(const struct device *psram)
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{
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const struct memc_mspi_aps6404l_config *cfg = psram->config;
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struct memc_mspi_aps6404l_data *data = psram->data;
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k_sem_take(&data->lock, K_FOREVER);
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if (cfg->sw_multi_periph) {
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while (mspi_dev_config(cfg->bus, &cfg->dev_id,
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MSPI_DEVICE_CONFIG_ALL, &data->dev_cfg)) {
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;
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}
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} else {
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while (mspi_dev_config(cfg->bus, &cfg->dev_id,
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MSPI_DEVICE_CONFIG_NONE, NULL)) {
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;
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}
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}
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}
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static void release(const struct device *psram)
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{
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const struct memc_mspi_aps6404l_config *cfg = psram->config;
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struct memc_mspi_aps6404l_data *data = psram->data;
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while (mspi_get_channel_status(cfg->bus, cfg->port)) {
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;
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}
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k_sem_give(&data->lock);
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}
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static int memc_mspi_aps6404l_reset(const struct device *psram)
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{
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int ret;
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LOG_DBG("Resetting aps6404l/%u", __LINE__);
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ret = memc_mspi_aps6404l_command_write(psram, APS6404L_RESET_ENABLE, 0, NULL, 0);
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if (ret) {
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return ret;
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}
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ret = memc_mspi_aps6404l_command_write(psram, APS6404L_RESET_MEMORY, 0, NULL, 0);
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if (ret) {
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return ret;
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}
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/** We need to delay 5 ms to allow aps6404L pSRAM to reinitialize */
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k_busy_wait(5000);
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return ret;
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}
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static int memc_mspi_aps6404l_get_vendor_id(const struct device *psram, uint8_t *vendor_id)
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{
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uint16_t buffer = 0;
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int ret;
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ret = memc_mspi_aps6404l_command_read(psram, APS6404L_READ_ID, 0, (uint8_t *)&buffer, 2);
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LOG_DBG("Read ID buff: %x/%u", buffer, __LINE__);
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*vendor_id = buffer & 0xff;
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return ret;
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}
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#if CONFIG_PM_DEVICE
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static int memc_mspi_aps6404l_half_sleep_enter(const struct device *psram)
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{
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int ret;
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LOG_DBG("Putting aps6404l to half sleep/%u", __LINE__);
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ret = memc_mspi_aps6404l_command_write(psram, APS6404L_HALF_SLEEP_ENTER, 0, NULL, 0);
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if (ret) {
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LOG_ERR("Failed to enter half sleep/%u", __LINE__);
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return ret;
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}
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/** Minimum half sleep duration tHS time */
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k_busy_wait(4);
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return ret;
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}
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static int memc_mspi_aps6404l_half_sleep_exit(const struct device *psram)
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{
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const struct memc_mspi_aps6404l_config *cfg = psram->config;
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struct memc_mspi_aps6404l_data *data = psram->data;
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struct mspi_dev_cfg bkp = data->dev_cfg;
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int ret = 0;
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data->dev_cfg.freq = 48000000;
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mspi_dev_config(cfg->bus, &cfg->dev_id, MSPI_DEVICE_CONFIG_FREQUENCY,
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(const struct mspi_dev_cfg *)&data->dev_cfg);
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LOG_DBG("Waking up aps6404l from half sleep/%u", __LINE__);
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ret = memc_mspi_aps6404l_command_write(psram, 0, 0, NULL, 0);
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if (ret) {
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LOG_ERR("Failed to exit from half sleep/%u", __LINE__);
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return ret;
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}
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/** Minimum half sleep exit CE to CLK setup time */
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k_busy_wait(100);
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data->dev_cfg = bkp;
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ret = mspi_dev_config(cfg->bus, &cfg->dev_id, MSPI_DEVICE_CONFIG_FREQUENCY,
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(const struct mspi_dev_cfg *)&data->dev_cfg);
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if (ret) {
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LOG_ERR("Failed to reconfigure MSPI after exiting half sleep/%u", __LINE__);
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return ret;
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}
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return ret;
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}
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static int memc_mspi_aps6404l_pm_action(const struct device *psram, enum pm_device_action action)
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{
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switch (action) {
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case PM_DEVICE_ACTION_RESUME:
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acquire(psram);
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memc_mspi_aps6404l_half_sleep_exit(psram);
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release(psram);
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break;
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case PM_DEVICE_ACTION_SUSPEND:
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acquire(psram);
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memc_mspi_aps6404l_half_sleep_enter(psram);
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release(psram);
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break;
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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#endif /** IS_ENABLED(CONFIG_PM_DEVICE) */
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static int memc_mspi_aps6404l_init(const struct device *psram)
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{
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const struct memc_mspi_aps6404l_config *cfg = psram->config;
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struct memc_mspi_aps6404l_data *data = psram->data;
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uint8_t vendor_id;
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if (!device_is_ready(cfg->bus)) {
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LOG_ERR("Controller device not ready/%u", __LINE__);
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return -ENODEV;
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}
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switch (cfg->tar_dev_cfg.io_mode) {
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case MSPI_IO_MODE_SINGLE:
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case MSPI_IO_MODE_QUAD:
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break;
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default:
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LOG_ERR("Bus mode %d not supported/%u", cfg->tar_dev_cfg.io_mode, __LINE__);
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return -EIO;
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}
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if (data->dev_cfg.io_mode == MSPI_IO_MODE_QUAD) {
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if (mspi_dev_config(cfg->bus, &cfg->dev_id, MSPI_DEVICE_CONFIG_ALL,
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&cfg->quad_cfg)) {
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LOG_ERR("Failed to config mspi controller/%u", __LINE__);
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return -EIO;
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}
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data->dev_cfg = cfg->quad_cfg;
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if (memc_mspi_aps6404l_reset(psram)) {
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LOG_ERR("Could not reset pSRAM/%u", __LINE__);
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return -EIO;
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}
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if (memc_mspi_aps6404l_command_write(psram, APS6404L_QUAD_MODE_EXIT, 0, NULL, 0)) {
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LOG_ERR("Could not exit quad mode/%u", __LINE__);
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return -EIO;
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}
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}
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if (mspi_dev_config(cfg->bus, &cfg->dev_id, MSPI_DEVICE_CONFIG_ALL, &cfg->serial_cfg)) {
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LOG_ERR("Failed to config mspi controller/%u", __LINE__);
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return -EIO;
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}
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data->dev_cfg = cfg->serial_cfg;
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if (memc_mspi_aps6404l_reset(psram)) {
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LOG_ERR("Could not reset pSRAM/%u", __LINE__);
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return -EIO;
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}
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if (memc_mspi_aps6404l_get_vendor_id(psram, &vendor_id)) {
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LOG_ERR("Could not read vendor id/%u", __LINE__);
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return -EIO;
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}
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LOG_DBG("Vendor id: 0x%0x", vendor_id);
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if (vendor_id != APM_VENDOR_ID) {
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LOG_WRN("Vendor ID does not match expected value of 0x%0x/%u", APM_VENDOR_ID,
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__LINE__);
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}
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if (cfg->tar_dev_cfg.io_mode == MSPI_IO_MODE_QUAD) {
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if (memc_mspi_aps6404l_command_write(psram, APS6404L_QUAD_MODE_ENTER, 0, NULL, 0)) {
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return -EIO;
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}
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}
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if (mspi_dev_config(cfg->bus, &cfg->dev_id, MSPI_DEVICE_CONFIG_ALL, &cfg->tar_dev_cfg)) {
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LOG_ERR("Failed to config mspi controller/%u", __LINE__);
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return -EIO;
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}
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data->dev_cfg = cfg->tar_dev_cfg;
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if (mspi_timing_config(cfg->bus, &cfg->dev_id, cfg->timing_cfg_mask,
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(void *)&cfg->tar_timing_cfg)) {
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LOG_ERR("Failed to config mspi timing/%u", __LINE__);
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return -EIO;
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}
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data->timing_cfg = cfg->tar_timing_cfg;
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if (cfg->tar_xip_cfg.enable) {
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if (mspi_xip_config(cfg->bus, &cfg->dev_id, &cfg->tar_xip_cfg)) {
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LOG_ERR("Failed to enable XIP/%u", __LINE__);
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return -EIO;
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}
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data->xip_cfg = cfg->tar_xip_cfg;
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}
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if (cfg->tar_scramble_cfg.enable) {
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if (mspi_scramble_config(cfg->bus, &cfg->dev_id, &cfg->tar_scramble_cfg)) {
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LOG_ERR("Failed to enable scrambling/%u", __LINE__);
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return -EIO;
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}
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data->scramble_cfg = cfg->tar_scramble_cfg;
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}
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release(psram);
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return 0;
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}
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#define MSPI_DEVICE_CONFIG_SERIAL(n) \
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{ \
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.ce_num = DT_INST_PROP(n, mspi_hardware_ce_num), \
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.freq = 12000000, \
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.io_mode = MSPI_IO_MODE_SINGLE, \
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.data_rate = MSPI_DATA_RATE_SINGLE, \
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.cpp = MSPI_CPP_MODE_0, \
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.endian = MSPI_XFER_LITTLE_ENDIAN, \
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.ce_polarity = MSPI_CE_ACTIVE_LOW, \
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.dqs_enable = false, \
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.rx_dummy = 8, \
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.tx_dummy = 0, \
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.read_cmd = APS6404L_FAST_READ, \
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.write_cmd = APS6404L_WRITE, \
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.cmd_length = 1, \
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.addr_length = 3, \
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.mem_boundary = 1024, \
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.time_to_break = 8, \
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}
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#define MSPI_DEVICE_CONFIG_QUAD(n) \
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{ \
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.ce_num = DT_INST_PROP(n, mspi_hardware_ce_num), \
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.freq = 24000000, \
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.io_mode = MSPI_IO_MODE_SINGLE, \
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.data_rate = MSPI_DATA_RATE_SINGLE, \
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.cpp = MSPI_CPP_MODE_0, \
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.endian = MSPI_XFER_LITTLE_ENDIAN, \
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.ce_polarity = MSPI_CE_ACTIVE_LOW, \
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.dqs_enable = false, \
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.rx_dummy = 6, \
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.tx_dummy = 0, \
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.read_cmd = APS6404L_QUAD_READ, \
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.write_cmd = APS6404L_QUAD_WRITE, \
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.cmd_length = 1, \
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.addr_length = 3, \
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.mem_boundary = 1024, \
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.time_to_break = 4, \
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}
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#if CONFIG_SOC_FAMILY_AMBIQ
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#define MSPI_TIMING_CONFIG(n) \
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{ \
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.ui8WriteLatency = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 0), \
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.ui8TurnAround = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 1), \
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.bTxNeg = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 2), \
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.bRxNeg = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 3), \
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.bRxCap = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 4), \
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.ui32TxDQSDelay = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 5), \
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.ui32RxDQSDelay = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 6), \
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.ui32RXDQSDelayEXT = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 7), \
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}
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#define MSPI_TIMING_CONFIG_MASK(n) DT_INST_PROP(n, ambiq_timing_config_mask)
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#else
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#define MSPI_TIMING_CONFIG(n)
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#define MSPI_TIMING_CONFIG_MASK(n)
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#endif
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#define MEMC_MSPI_APS6404L(n) \
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static const struct memc_mspi_aps6404l_config \
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memc_mspi_aps6404l_config_##n = { \
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.port = MSPI_PORT(n), \
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.mem_size = DT_INST_PROP(n, size) / 8, \
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.bus = DEVICE_DT_GET(DT_INST_BUS(n)), \
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.dev_id = MSPI_DEVICE_ID_DT_INST(n), \
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.serial_cfg = MSPI_DEVICE_CONFIG_SERIAL(n), \
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.quad_cfg = MSPI_DEVICE_CONFIG_QUAD(n), \
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.tar_dev_cfg = MSPI_DEVICE_CONFIG_DT_INST(n), \
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.tar_xip_cfg = MSPI_XIP_CONFIG_DT_INST(n), \
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.tar_scramble_cfg = MSPI_SCRAMBLE_CONFIG_DT_INST(n), \
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.tar_timing_cfg = MSPI_TIMING_CONFIG(n), \
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.timing_cfg_mask = MSPI_TIMING_CONFIG_MASK(n), \
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.sw_multi_periph = DT_PROP(DT_INST_BUS(n), software_multiperipheral) \
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}; \
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static struct memc_mspi_aps6404l_data \
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memc_mspi_aps6404l_data_##n = { \
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.lock = Z_SEM_INITIALIZER(memc_mspi_aps6404l_data_##n.lock, 0, 1), \
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}; \
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PM_DEVICE_DT_INST_DEFINE(n, memc_mspi_aps6404l_pm_action); \
|
|
DEVICE_DT_INST_DEFINE(n, \
|
|
memc_mspi_aps6404l_init, \
|
|
PM_DEVICE_DT_INST_GET(n), \
|
|
&memc_mspi_aps6404l_data_##n, \
|
|
&memc_mspi_aps6404l_config_##n, \
|
|
POST_KERNEL, \
|
|
CONFIG_MEMC_INIT_PRIORITY, \
|
|
NULL);
|
|
|
|
DT_INST_FOREACH_STATUS_OKAY(MEMC_MSPI_APS6404L)
|