117 lines
3.4 KiB
C
117 lines
3.4 KiB
C
/* SPDX-License-Identifier: Apache-2.0 */
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/*
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* Copyright © 2023 Calian Ltd. All rights reserved.
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*
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* Driver for the Xilinx AXI IIC Bus Interface.
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* This is an FPGA logic core as described by Xilinx document PG090.
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*/
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#ifndef ZEPHYR_DRIVERS_I2C_I2C_XILINX_AXI_H_
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#define ZEPHYR_DRIVERS_I2C_I2C_XILINX_AXI_H_
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#include <zephyr/sys/util_macro.h>
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/* Register offsets */
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enum xilinx_axi_i2c_register {
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REG_GIE = 0x01C, /* Global Interrupt Enable */
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REG_ISR = 0x020, /* Interrupt Status */
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REG_IER = 0x028, /* Interrupt Enable */
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REG_SOFTR = 0x040, /* Soft Reset */
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REG_CR = 0x100, /* Control */
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REG_SR = 0x104, /* Status */
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REG_TX_FIFO = 0x108, /* Transmit FIFO */
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REG_RX_FIFO = 0x10C, /* Receive FIFO */
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REG_ADR = 0x110, /* Target Address */
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REG_TX_FIFO_OCY = 0x114, /* Transmit FIFO Occupancy */
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REG_RX_FIFO_OCY = 0x118, /* Receive FIFO Occupancy */
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REG_TEN_ADR = 0x11C, /* Target Ten Bit Address */
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REG_RX_FIFO_PIRQ = 0x120, /* Receive FIFO Programmable Depth Interrupt */
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REG_GPO = 0x124, /* General Purpose Output */
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REG_TSUSTA = 0x128, /* Timing Parameter */
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REG_TSUSTO = 0x12C, /* Timing Parameter */
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REG_THDSTA = 0x130, /* Timing Parameter */
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REG_TSUDAT = 0x134, /* Timing Parameter */
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REG_TBUF = 0x138, /* Timing Parameter */
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REG_THIGH = 0x13C, /* Timing Parameter */
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REG_TLOW = 0x140, /* Timing Parameter */
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REG_THDDAT = 0x144, /* Timing Parameter */
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};
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/* Register bits */
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/* Global Interrupt Enable */
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enum xilinx_axi_i2c_gie_bits {
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GIE_ENABLE = BIT(31),
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};
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/* Interrupt Status/Interrupt Enable */
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enum xilinx_axi_i2c_isr_bits {
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ISR_TX_HALF_EMPTY = BIT(7), /* Transmit FIFO Half Empty */
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ISR_NOT_ADDR_TARGET = BIT(6), /* Not Addressed As Target */
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ISR_ADDR_TARGET = BIT(5), /* Addressed As Target */
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ISR_BUS_NOT_BUSY = BIT(4), /* IIC Bus is Not Busy */
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ISR_RX_FIFO_FULL = BIT(3), /* Receive FIFO Full */
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ISR_TX_FIFO_EMPTY = BIT(2), /* Transmit FIFO Empty */
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ISR_TX_ERR_TARGET_COMP = BIT(1), /* Transmit Error/Target Transmit Complete */
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ISR_ARB_LOST = BIT(0), /* Arbitration Lost */
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};
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/* Soft Reset */
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enum xilinx_axi_i2c_softr_vals {
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SOFTR_KEY = 0xA,
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};
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/* Control */
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enum xilinx_axi_i2c_cr_bits {
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CR_GC_EN = BIT(6), /* General Call Enable */
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CR_RSTA = BIT(5), /* Repeated Start */
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CR_TXAK = BIT(4), /* Transmit Acknowledge Enable */
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CR_TX = BIT(3), /* Transmit/Receive Mode Select */
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CR_MSMS = BIT(2), /* Controller/Target Mode Select */
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CR_TX_FIFO_RST = BIT(1), /* Transmit FIFO Reset */
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CR_EN = BIT(0), /* AXI IIC Enable */
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};
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/* Status */
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enum xilinx_axi_i2c_sr_bits {
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SR_TX_FIFO_EMPTY = BIT(7), /* Transmit FIFO empty */
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SR_RX_FIFO_EMPTY = BIT(6), /* Receive FIFO empty */
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SR_RX_FIFO_FULL = BIT(5), /* Receive FIFO full */
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SR_TX_FIFO_FULL = BIT(4), /* Transmit FIFO full */
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SR_SRW = BIT(3), /* Target Read/Write */
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SR_BB = BIT(2), /* Bus Busy */
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SR_AAS = BIT(1), /* Addressed As Target */
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SR_ABGC = BIT(0), /* Addressed By a General Call */
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};
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/* TX FIFO */
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enum xilinx_axi_i2c_tx_fifo_bits {
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TX_FIFO_STOP = BIT(9),
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TX_FIFO_START = BIT(8),
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};
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/* RX FIFO */
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enum xilinx_axi_i2c_rx_fifo_bits {
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RX_FIFO_DATA_MASK = 0xFF,
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};
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/* TX_FIFO_OCY */
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enum xilinx_axi_i2c_tx_fifo_ocy_bits {
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TX_FIFO_OCY_MASK = 0x0F,
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};
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/* RX_FIFO_OCY */
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enum xilinx_axi_i2c_rx_fifo_ocy_bits {
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RX_FIFO_OCY_MASK = 0x0F,
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};
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/* other constants */
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enum {
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/* Size of RX/TX FIFO */
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FIFO_SIZE = 16,
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/* Maximum number of bytes that can be read in dynamic mode */
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MAX_DYNAMIC_READ_LEN = 255,
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};
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#endif
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