89 lines
2.4 KiB
C
89 lines
2.4 KiB
C
/*
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* Copyright (c) 2023 Nuvoton Technology Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_FLASH_NPCX_FIU_QSPI_H_
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#define ZEPHYR_DRIVERS_FLASH_NPCX_FIU_QSPI_H_
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#include <zephyr/device.h>
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#include "jesd216.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* UMA operation flags */
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#define NPCX_UMA_ACCESS_WRITE BIT(0)
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#define NPCX_UMA_ACCESS_READ BIT(1)
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#define NPCX_UMA_ACCESS_ADDR BIT(2)
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/* Valid value of Dn_NADDRB that sets the number of address bytes in a transaction */
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#define NPCX_DEV_NUM_ADDR_1BYTE 1
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#define NPCX_DEV_NUM_ADDR_2BYTE 2
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#define NPCX_DEV_NUM_ADDR_3BYTE 3
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#define NPCX_DEV_NUM_ADDR_4BYTE 4
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/* UMA operation configuration for a SPI device */
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struct npcx_uma_cfg {
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uint8_t opcode;
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uint8_t *tx_buf;
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size_t tx_count;
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uint8_t *rx_buf;
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size_t rx_count;
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union {
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uint32_t u32;
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uint8_t u8[4];
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} addr;
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};
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/* QSPI bus configuration for a SPI device */
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struct npcx_qspi_cfg {
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/* Type of Quad Enable bit in status register */
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enum jesd216_dw15_qer_type qer_type;
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/* Pinctrl for QSPI bus */
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const struct pinctrl_dev_config *pcfg;
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/* Enter four bytes address mode value */
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uint8_t enter_4ba;
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/* SPI read access type of Direct Read Access mode */
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uint8_t rd_mode;
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/* Configurations for the Quad-SPI peripherals */
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int flags;
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};
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/**
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* @brief Execute UMA transactions on qspi bus
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*
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* @param dev Pointer to the device structure for qspi bus controller instance.
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* @param cfg Pointer to the configuration of UMA transactions.
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* @param flags Flags to be used during transactions.
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* @retval 0 on success, -EPERM if an UMA transaction is not permitted.
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*/
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int qspi_npcx_fiu_uma_transceive(const struct device *dev, struct npcx_uma_cfg *cfg,
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uint32_t flags);
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/**
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* @brief Lock the mutex of npcx qspi bus controller and apply its configuration
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*
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* @param dev Pointer to the device structure for qspi bus controller instance.
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* @param cfg Pointer to the configuration for the device on qspi bus.
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* @param operation Qspi bus operation for the device.
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*/
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void qspi_npcx_fiu_mutex_lock_configure(const struct device *dev,
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const struct npcx_qspi_cfg *cfg,
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const uint32_t operation);
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/**
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* @brief Unlock the mutex of npcx qspi bus controller.
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*
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* @param dev Pointer to the device structure for qspi bus controller instance.
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*/
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void qspi_npcx_fiu_mutex_unlock(const struct device *dev);
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_DRIVERS_FLASH_NPCX_FIU_QSPI_H_ */
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