160 lines
5.7 KiB
C
160 lines
5.7 KiB
C
/*
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* Copyright (c) 2023 Arm Limited (or its affiliates). All rights reserved.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_ETHERNET_ETH_SMSC91X_PRIV_H_
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#define ZEPHYR_DRIVERS_ETHERNET_ETH_SMSC91X_PRIV_H_
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#include <zephyr/sys/util.h>
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/* All Banks, Offset 0xe: Bank Select Register */
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#define BSR 0xe
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#define BSR_BANK_MASK GENMASK(2, 0) /* Which bank is currently selected */
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#define BSR_IDENTIFY 0x33
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#define BSR_IDENTIFY_MASK GENMASK(15, 8)
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/* Bank 0, Offset 0x0: Transmit Control Register */
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#define TCR 0x0
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#define TCR_TXENA 0x0001 /* Enable/disable transmitter */
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#define TCR_PAD_EN 0x0080 /* Pad TX frames to 64 bytes */
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/* Bank 0, Offset 0x02: EPH status register */
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#define EPHSR 0x2
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#define EPHSR_TX_SUC 0x0001 /* Last TX was successful */
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/* Bank 0, Offset 0x4: Receive Control Register */
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#define RCR 0x4
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#define RCR_PRMS 0x0002 /* Promiscuous mode */
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#define RCR_RXEN 0x0100 /* Enable/disable receiver */
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#define RCR_STRIP_CRC 0x0200 /* Strip CRC from RX packets */
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#define RCR_SOFT_RST 0x8000 /* Software reset */
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/* Bank0, Offset 0x6: Counter Register */
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#define ECR 0x6
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#define ECR_SNGLCOL_MASK GENMASK(3, 0) /* Single collisions */
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#define ECR_MULCOL_MASK GENMASK(7, 4) /* Multiple collisions */
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#define ECR_TX_DEFR_MASK GENMASK(11, 8) /* Transmit deferrals */
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#define ECR_EXC_DEFR_MASK GENMASK(15, 12) /* Excessive deferrals */
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/* Bank 0, Offset 0x8: Memory information register */
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#define MIR 0x8
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#define MIR_SIZE_MASK GENMASK(7, 0) /* Memory size (2k pages) */
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#define MIR_FREE_MASK GENMASK(15, 8) /* Memory free (2k pages) */
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/* bank 0, offset 0xa: receive/phy control register */
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#define RPCR 0xa
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#define RPCR_ANEG 0x0800 /* Put PHY in autonegotiation mode */
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#define RPCR_DPLX 0x1000 /* Put PHY in full-duplex mode */
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#define RPCR_SPEED 0x2000 /* Manual speed selection */
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#define RPCR_LSA_MASK GENMASK(7, 5)
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#define RPCR_LSB_MASK GENMASK(4, 2)
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#define RPCR_LED_LINK_ANY 0x0 /* 10baseT or 100baseTX link detected */
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#define RPCR_LED_LINK_10 0x2 /* 10baseT link detected */
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#define RPCR_LED_LINK_FDX 0x3 /* Full-duplex link detect */
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#define RPCR_LED_LINK_100 0x5 /* 100baseTX link detected */
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#define RPCR_LED_ACT_ANY 0x4 /* TX or RX activity detected */
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#define RPCR_LED_ACT_RX 0x6 /* RX activity detected */
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#define RPCR_LED_ACT_TX 0x7 /* TX activity detected */
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/* Bank 1, Offset 0x0: Configuration Register */
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#define CR 0x0
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#define CR_EPH_POWER_EN 0x8000 /* Disable/enable low power mode */
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/* Bank 1, Offset 0x2: Base Address Register */
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#define BAR 0x2
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/* Bank 1, Offsets 0x4: Individual Address Registers */
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#define IAR0 0x4
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#define IAR1 0x5
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#define IAR2 0x6
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#define IAR3 0x7
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#define IAR4 0x8
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#define IAR5 0x9
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/* Bank 1, Offset 0xc: Control Register */
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#define CTR 0xc
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#define CTR_LE_ENABLE 0x0080 /* Link error causes EPH interrupt */
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#define CTR_AUTO_RELEASE 0x0800 /* Automatically release TX packets */
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/* Bank 2, Offset 0x0: MMU Command Register */
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#define MMUCR 0x0
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#define MMUCR_BUSY 0x0001 /* MMU is busy */
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#define MMUCR_CMD_MASK GENMASK(7, 5) /* MMU command mask */
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#define MMUCR_CMD_TX_ALLOC 1 /* Alloc TX memory (256b chunks) */
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#define MMUCR_CMD_MMU_RESET 2 /* Reset MMU */
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#define MMUCR_CMD_RELEASE 4 /* Remove and release from RX FIFO */
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#define MMUCR_CMD_RELEASE_PKT 5 /* Release packet specified in PNR */
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#define MMUCR_CMD_ENQUEUE 6 /* Enqueue packet for TX */
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/* Bank2, Offset 0x2: Packet Number Register */
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#define PNR 0x2
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#define PNR_MASK GENMASK(5, 0)
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/* Bank2, Offset 0x3: Allocation Result Register */
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#define ARR 0x3
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#define ARR_FAILED 0x80
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#define ARR_MASK GENMASK(5, 0)
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/* Bank 2, Offset 0x4: FIFO Ports Register */
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#define FIFO 0x04
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#define FIFO_TX 0x4
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#define FIFO_RX 0x5
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#define FIFO_EMPTY 0x80 /* FIFO empty */
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#define FIFO_PACKET_MASK GENMASK(5, 0) /* Packet number mask */
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/* Bank2, Offset 0x6: Point Register */
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#define PTR 0x6
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#define PTR_MASK GENMASK(10, 0) /* Address accessible within TX/RX */
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#define PTR_NOT_EMPTY 0x0800 /* Write Data FIFO not empty */
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#define PTR_READ 0x2000 /* Set read/write */
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#define PTR_AUTO_INCR 0x4000 /* Auto increment on read/write */
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#define PTR_RCV 0x8000 /* Read/write to/from RX/TX */
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/* Bank2, Offset 0x8: Data register */
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#define DATA0 0x8
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#define DATA1 0xa
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/* Bank 2, Offset 0xc: Interrupt Status Registers */
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#define IST 0xc /* read only */
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#define ACK 0xc /* write only */
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#define MSK 0xd
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#define RCV_INT 0x0001 /* RX */
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#define TX_INT 0x0002 /* TX */
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#define TX_EMPTY_INT 0x0004 /* TX empty */
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#define ALLOC_INT 0x0008 /* Allocation complete */
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#define RX_OVRN_INT 0x0010 /* RX overrun */
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#define EPH_INT 0x0020 /* EPH interrupt */
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#define ERCV_INT 0x0040 /* Early RX */
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#define MD_INT 0x0080 /* MII */
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/* Bank 3, Offset 0x8: Management interface register */
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#define MGMT 0x8
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#define MGMT_MDO 0x0001 /* MII management output */
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#define MGMT_MDI 0x0002 /* MII management input */
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#define MGMT_MCLK 0x0004 /* MII management clock */
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#define MGMT_MDOE 0x0008 /* MII management output enable */
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/* Bank 3, Offset 0xa: Revision Register */
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#define REV 0xa
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#define REV_CHIP_MASK GENMASK(7, 4)
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#define REV_REV_MASK GENMASK(3, 0)
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/* Control Byte */
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#define CTRL_CRC 0x10 /* Frame has CRC */
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#define CTRL_ODD 0x20 /* Frame has odd bytes count */
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/* Receive frame status */
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#define RX_TOOSHORT 0x0400 /* Frame was too short */
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#define RX_TOOLNG 0x0800 /* Frame was too long */
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#define RX_ODDFRM 0x1000 /* Frame has odd number of bytes */
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#define RX_BADCRC 0x2000 /* Frame failed CRC */
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#define RX_ALIGNERR 0x8000 /* Frame has alignment error */
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#define RX_LEN_MASK GENMASK(10, 0)
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/* Length of status word + byte count + control bytes for packets */
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#define PKT_CTRL_DATA_LEN 6
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#endif
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