702 lines
19 KiB
C
702 lines
19 KiB
C
/*
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* Copyright (c) 2018 Workaround GmbH
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* Copyright (c) 2018 Allterco Robotics
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* Copyright (c) 2018 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Source file for the STM32 RTC driver
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*
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*/
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#define DT_DRV_COMPAT st_stm32_rtc
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#include <time.h>
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#include <zephyr/drivers/clock_control/stm32_clock_control.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/kernel.h>
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#include <soc.h>
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#include <stm32_ll_exti.h>
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#include <stm32_ll_pwr.h>
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#include <stm32_ll_rcc.h>
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#include <stm32_ll_rtc.h>
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#include <zephyr/drivers/counter.h>
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#include <zephyr/sys/timeutil.h>
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#include <zephyr/pm/device.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/irq.h>
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#include "stm32_hsem.h"
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LOG_MODULE_REGISTER(counter_rtc_stm32, CONFIG_COUNTER_LOG_LEVEL);
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/* Seconds from 1970-01-01T00:00:00 to 2000-01-01T00:00:00 */
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#define T_TIME_OFFSET 946684800
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#if defined(CONFIG_SOC_SERIES_STM32L4X)
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#define RTC_EXTI_LINE LL_EXTI_LINE_18
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#elif defined(CONFIG_SOC_SERIES_STM32C0X) \
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|| defined(CONFIG_SOC_SERIES_STM32G0X)
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#define RTC_EXTI_LINE LL_EXTI_LINE_19
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#elif defined(CONFIG_SOC_SERIES_STM32F4X) \
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|| defined(CONFIG_SOC_SERIES_STM32F0X) \
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|| defined(CONFIG_SOC_SERIES_STM32F1X) \
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|| defined(CONFIG_SOC_SERIES_STM32F2X) \
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|| defined(CONFIG_SOC_SERIES_STM32F3X) \
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|| defined(CONFIG_SOC_SERIES_STM32F7X) \
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|| defined(CONFIG_SOC_SERIES_STM32WBX) \
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|| defined(CONFIG_SOC_SERIES_STM32G4X) \
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|| defined(CONFIG_SOC_SERIES_STM32L0X) \
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|| defined(CONFIG_SOC_SERIES_STM32L1X) \
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|| defined(CONFIG_SOC_SERIES_STM32L5X) \
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|| defined(CONFIG_SOC_SERIES_STM32H7X) \
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|| defined(CONFIG_SOC_SERIES_STM32H5X) \
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|| defined(CONFIG_SOC_SERIES_STM32WLX)
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#define RTC_EXTI_LINE LL_EXTI_LINE_17
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#endif
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#if defined(CONFIG_SOC_SERIES_STM32F1X)
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#define COUNTER_NO_DATE
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#endif
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#if DT_INST_CLOCKS_CELL_BY_IDX(0, 1, bus) == STM32_SRC_LSI
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/* LSI */
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#define RTCCLK_FREQ STM32_LSI_FREQ
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#else
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/* LSE */
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#define RTCCLK_FREQ STM32_LSE_FREQ
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#endif /* DT_INST_CLOCKS_CELL_BY_IDX(0, 1, bus) == STM32_SRC_LSI */
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#if !defined(CONFIG_SOC_SERIES_STM32F1X)
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#ifndef CONFIG_COUNTER_RTC_STM32_SUBSECONDS
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#define RTC_ASYNCPRE BIT_MASK(7)
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#else /* !CONFIG_COUNTER_RTC_STM32_SUBSECONDS */
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/* Get the highest possible clock for the subsecond register */
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#define RTC_ASYNCPRE 1
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#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS */
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#else /* CONFIG_SOC_SERIES_STM32F1X */
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#define RTC_ASYNCPRE (RTCCLK_FREQ - 1)
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#endif /* CONFIG_SOC_SERIES_STM32F1X */
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/* Adjust the second sync prescaler to get 1Hz on ck_spre */
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#define RTC_SYNCPRE ((RTCCLK_FREQ / (1 + RTC_ASYNCPRE)) - 1)
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#ifndef CONFIG_COUNTER_RTC_STM32_SUBSECONDS
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typedef uint32_t tick_t;
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#else
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typedef uint64_t tick_t;
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#endif
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struct rtc_stm32_config {
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struct counter_config_info counter_info;
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LL_RTC_InitTypeDef ll_rtc_config;
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const struct stm32_pclken *pclken;
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};
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struct rtc_stm32_data {
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counter_alarm_callback_t callback;
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uint32_t ticks;
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void *user_data;
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#ifdef CONFIG_COUNTER_RTC_STM32_SUBSECONDS
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bool irq_on_late;
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#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS */
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};
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static inline ErrorStatus ll_func_init_alarm(RTC_TypeDef *rtc, uint32_t format,
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LL_RTC_AlarmTypeDef *alarmStruct)
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{
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#if defined(CONFIG_SOC_SERIES_STM32F1X)
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return LL_RTC_ALARM_Init(rtc, format, alarmStruct);
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#else
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return LL_RTC_ALMA_Init(rtc, format, alarmStruct);
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#endif
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}
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static inline void ll_func_clear_alarm_flag(RTC_TypeDef *rtc)
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{
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#if defined(CONFIG_SOC_SERIES_STM32F1X)
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LL_RTC_ClearFlag_ALR(rtc);
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#else
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LL_RTC_ClearFlag_ALRA(rtc);
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#endif
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}
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static inline uint32_t ll_func_is_active_alarm(RTC_TypeDef *rtc)
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{
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#if defined(CONFIG_SOC_SERIES_STM32F1X)
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return LL_RTC_IsActiveFlag_ALR(rtc);
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#else
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return LL_RTC_IsActiveFlag_ALRA(rtc);
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#endif
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}
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static inline void ll_func_enable_interrupt_alarm(RTC_TypeDef *rtc)
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{
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#if defined(CONFIG_SOC_SERIES_STM32F1X)
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LL_RTC_EnableIT_ALR(rtc);
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#else
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LL_RTC_EnableIT_ALRA(rtc);
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#endif
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}
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static inline void ll_func_disable_interrupt_alarm(RTC_TypeDef *rtc)
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{
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#if defined(CONFIG_SOC_SERIES_STM32F1X)
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LL_RTC_DisableIT_ALR(rtc);
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#else
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LL_RTC_DisableIT_ALRA(rtc);
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#endif
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}
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#ifdef CONFIG_COUNTER_RTC_STM32_SUBSECONDS
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static inline uint32_t ll_func_isenabled_interrupt_alarm(RTC_TypeDef *rtc)
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{
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#if defined(CONFIG_SOC_SERIES_STM32F1X)
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return LL_RTC_IsEnabledIT_ALR(rtc);
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#else
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return LL_RTC_IsEnabledIT_ALRA(rtc);
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#endif
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}
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#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS */
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static inline void ll_func_enable_alarm(RTC_TypeDef *rtc)
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{
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#if defined(CONFIG_SOC_SERIES_STM32F1X)
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ARG_UNUSED(rtc);
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#else
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LL_RTC_ALMA_Enable(rtc);
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#endif
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}
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static inline void ll_func_disable_alarm(RTC_TypeDef *rtc)
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{
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#if defined(CONFIG_SOC_SERIES_STM32F1X)
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ARG_UNUSED(rtc);
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#else
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LL_RTC_ALMA_Disable(rtc);
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#endif
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}
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static void rtc_stm32_irq_config(const struct device *dev);
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static int rtc_stm32_start(const struct device *dev)
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{
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#if defined(CONFIG_SOC_SERIES_STM32WBAX) || defined(CONFIG_SOC_SERIES_STM32U5X)
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const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
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const struct rtc_stm32_config *cfg = dev->config;
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/* Enable RTC bus clock */
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if (clock_control_on(clk, (clock_control_subsys_t) &cfg->pclken[0]) != 0) {
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LOG_ERR("RTC clock enabling failed\n");
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return -EIO;
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}
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#else
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ARG_UNUSED(dev);
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z_stm32_hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
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LL_RCC_EnableRTC();
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z_stm32_hsem_unlock(CFG_HW_RCC_SEMID);
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#endif
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return 0;
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}
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static int rtc_stm32_stop(const struct device *dev)
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{
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#if defined(CONFIG_SOC_SERIES_STM32WBAX) || defined(CONFIG_SOC_SERIES_STM32U5X)
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const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
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const struct rtc_stm32_config *cfg = dev->config;
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/* Disable RTC bus clock */
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if (clock_control_off(clk, (clock_control_subsys_t) &cfg->pclken[0]) != 0) {
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LOG_ERR("RTC clock disabling failed\n");
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return -EIO;
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}
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#else
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ARG_UNUSED(dev);
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z_stm32_hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
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LL_RCC_DisableRTC();
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z_stm32_hsem_unlock(CFG_HW_RCC_SEMID);
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#endif
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return 0;
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}
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#if !defined(COUNTER_NO_DATE)
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tick_t rtc_stm32_read(const struct device *dev)
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{
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struct tm now = { 0 };
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time_t ts;
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uint32_t rtc_date, rtc_time;
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tick_t ticks;
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#ifdef CONFIG_COUNTER_RTC_STM32_SUBSECONDS
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uint32_t rtc_subseconds;
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#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS */
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ARG_UNUSED(dev);
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/* Enable Backup access */
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#if defined(PWR_CR_DBP) || defined(PWR_CR1_DBP) || \
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defined(PWR_DBPCR_DBP) || defined(PWR_DBPR_DBP)
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LL_PWR_EnableBkUpAccess();
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#endif /* PWR_CR_DBP || PWR_CR1_DBP || PWR_DBPR_DBP */
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/* Read time and date registers. Make sure value of the previous register
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* hasn't been changed while reading the next one.
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*/
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do {
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rtc_date = LL_RTC_DATE_Get(RTC);
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#ifdef CONFIG_COUNTER_RTC_STM32_SUBSECONDS
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do {
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rtc_time = LL_RTC_TIME_Get(RTC);
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rtc_subseconds = LL_RTC_TIME_GetSubSecond(RTC);
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} while (rtc_time != LL_RTC_TIME_Get(RTC));
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#else /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS */
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rtc_time = LL_RTC_TIME_Get(RTC);
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#endif
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} while (rtc_date != LL_RTC_DATE_Get(RTC));
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/* Convert calendar datetime to UNIX timestamp */
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/* RTC start time: 1st, Jan, 2000 */
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/* time_t start: 1st, Jan, 1970 */
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now.tm_year = 100 +
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__LL_RTC_CONVERT_BCD2BIN(__LL_RTC_GET_YEAR(rtc_date));
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/* tm_mon allowed values are 0-11 */
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now.tm_mon = __LL_RTC_CONVERT_BCD2BIN(__LL_RTC_GET_MONTH(rtc_date)) - 1;
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now.tm_mday = __LL_RTC_CONVERT_BCD2BIN(__LL_RTC_GET_DAY(rtc_date));
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now.tm_hour = __LL_RTC_CONVERT_BCD2BIN(__LL_RTC_GET_HOUR(rtc_time));
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now.tm_min = __LL_RTC_CONVERT_BCD2BIN(__LL_RTC_GET_MINUTE(rtc_time));
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now.tm_sec = __LL_RTC_CONVERT_BCD2BIN(__LL_RTC_GET_SECOND(rtc_time));
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ts = timeutil_timegm(&now);
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/* Return number of seconds since RTC init */
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ts -= T_TIME_OFFSET;
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__ASSERT(sizeof(time_t) == 8, "unexpected time_t definition");
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ticks = ts * counter_get_frequency(dev);
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#ifdef CONFIG_COUNTER_RTC_STM32_SUBSECONDS
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/* The RTC counts up, except for the subsecond register which counts
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* down starting from the sync prescaler value. Add already counted
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* ticks.
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*/
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ticks += RTC_SYNCPRE - rtc_subseconds;
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#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS */
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return ticks;
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}
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#else /* defined(COUNTER_NO_DATE) */
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tick_t rtc_stm32_read(const struct device *dev)
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{
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uint32_t rtc_time, ticks;
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ARG_UNUSED(dev);
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/* Enable Backup access */
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#if defined(PWR_CR_DBP) || defined(PWR_CR1_DBP) || \
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defined(PWR_DBPCR_DBP) || defined(PWR_DBPR_DBP)
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LL_PWR_EnableBkUpAccess();
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#endif /* PWR_CR_DBP || PWR_CR1_DBP || PWR_DBPR_DBP */
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rtc_time = LL_RTC_TIME_Get(RTC);
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ticks = rtc_time;
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return ticks;
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}
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#endif /* !defined(COUNTER_NO_DATE) */
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static int rtc_stm32_get_value(const struct device *dev, uint32_t *ticks)
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{
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*ticks = (uint32_t)rtc_stm32_read(dev);
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return 0;
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}
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#ifdef CONFIG_COUNTER_RTC_STM32_SUBSECONDS
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static int rtc_stm32_get_value_64(const struct device *dev, uint64_t *ticks)
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{
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*ticks = rtc_stm32_read(dev);
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return 0;
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}
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#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS */
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#ifdef CONFIG_COUNTER_RTC_STM32_SUBSECONDS
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static void rtc_stm32_set_int_pending(void)
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{
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NVIC_SetPendingIRQ(DT_INST_IRQN(0));
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}
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#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS */
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static int rtc_stm32_set_alarm(const struct device *dev, uint8_t chan_id,
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const struct counter_alarm_cfg *alarm_cfg)
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{
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#if !defined(COUNTER_NO_DATE)
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struct tm alarm_tm;
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time_t alarm_val_s;
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#ifdef CONFIG_COUNTER_RTC_STM32_SUBSECONDS
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uint32_t alarm_val_ss;
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#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS */
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#else
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uint32_t remain;
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#endif
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LL_RTC_AlarmTypeDef rtc_alarm;
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struct rtc_stm32_data *data = dev->data;
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tick_t now = rtc_stm32_read(dev);
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tick_t ticks = alarm_cfg->ticks;
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if (data->callback != NULL) {
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LOG_DBG("Alarm busy\n");
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return -EBUSY;
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}
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data->callback = alarm_cfg->callback;
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data->user_data = alarm_cfg->user_data;
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#if !defined(COUNTER_NO_DATE)
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if ((alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE) == 0) {
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/* Add +1 in order to compensate the partially started tick.
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* Alarm will expire between requested ticks and ticks+1.
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* In case only 1 tick is requested, it will avoid
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* that tick+1 event occurs before alarm setting is finished.
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*/
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ticks += now + 1;
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alarm_val_s = (time_t)(ticks / counter_get_frequency(dev)) + T_TIME_OFFSET;
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} else {
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alarm_val_s = (time_t)(ticks / counter_get_frequency(dev));
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}
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#ifdef CONFIG_COUNTER_RTC_STM32_SUBSECONDS
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alarm_val_ss = ticks % counter_get_frequency(dev);
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#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS */
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#else
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if ((alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE) == 0) {
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remain = ticks + now + 1;
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} else {
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remain = ticks;
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}
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/* In F1X, an interrupt occurs when the counter expires,
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* not when the counter matches, so set -1
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*/
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remain--;
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#endif
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#if !defined(COUNTER_NO_DATE)
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#ifndef CONFIG_COUNTER_RTC_STM32_SUBSECONDS
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LOG_DBG("Set Alarm: %d\n", ticks);
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#else /* !CONFIG_COUNTER_RTC_STM32_SUBSECONDS */
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LOG_DBG("Set Alarm: %llu\n", ticks);
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#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS */
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gmtime_r(&alarm_val_s, &alarm_tm);
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/* Apply ALARM_A */
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rtc_alarm.AlarmTime.TimeFormat = LL_RTC_TIME_FORMAT_AM_OR_24;
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rtc_alarm.AlarmTime.Hours = alarm_tm.tm_hour;
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rtc_alarm.AlarmTime.Minutes = alarm_tm.tm_min;
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rtc_alarm.AlarmTime.Seconds = alarm_tm.tm_sec;
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rtc_alarm.AlarmMask = LL_RTC_ALMA_MASK_NONE;
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rtc_alarm.AlarmDateWeekDaySel = LL_RTC_ALMA_DATEWEEKDAYSEL_DATE;
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rtc_alarm.AlarmDateWeekDay = alarm_tm.tm_mday;
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#else
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rtc_alarm.AlarmTime.Hours = remain / 3600;
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remain -= rtc_alarm.AlarmTime.Hours * 3600;
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rtc_alarm.AlarmTime.Minutes = remain / 60;
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remain -= rtc_alarm.AlarmTime.Minutes * 60;
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rtc_alarm.AlarmTime.Seconds = remain;
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#endif
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LL_RTC_DisableWriteProtection(RTC);
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ll_func_disable_alarm(RTC);
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LL_RTC_EnableWriteProtection(RTC);
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if (ll_func_init_alarm(RTC, LL_RTC_FORMAT_BIN, &rtc_alarm) != SUCCESS) {
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return -EIO;
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}
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LL_RTC_DisableWriteProtection(RTC);
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#ifdef CONFIG_COUNTER_RTC_STM32_SUBSECONDS
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/* Care about all bits of the subsecond register */
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LL_RTC_ALMA_SetSubSecondMask(RTC, 0xF);
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LL_RTC_ALMA_SetSubSecond(RTC, RTC_SYNCPRE - alarm_val_ss);
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#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS */
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ll_func_enable_alarm(RTC);
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ll_func_clear_alarm_flag(RTC);
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ll_func_enable_interrupt_alarm(RTC);
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LL_RTC_EnableWriteProtection(RTC);
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#ifdef CONFIG_COUNTER_RTC_STM32_SUBSECONDS
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/* The reference manual says:
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* "Each change of the RTC_CR register is taken into account after
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* 1 to 2 RTCCLK clock cycles due to clock synchronization."
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* It means we need at least two cycles after programming the CR
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* register. It is confirmed experimentally.
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*
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* It should happen only if one tick alarm is requested and a tick
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* occurs while processing the function. Trigger the irq manually in
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* this case.
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*/
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now = rtc_stm32_read(dev);
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if ((ticks - now < 2) || (now > ticks)) {
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data->irq_on_late = 1;
|
|
rtc_stm32_set_int_pending();
|
|
}
|
|
#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS */
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
static int rtc_stm32_cancel_alarm(const struct device *dev, uint8_t chan_id)
|
|
{
|
|
struct rtc_stm32_data *data = dev->data;
|
|
|
|
LL_RTC_DisableWriteProtection(RTC);
|
|
ll_func_clear_alarm_flag(RTC);
|
|
ll_func_disable_interrupt_alarm(RTC);
|
|
ll_func_disable_alarm(RTC);
|
|
LL_RTC_EnableWriteProtection(RTC);
|
|
|
|
data->callback = NULL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
static uint32_t rtc_stm32_get_pending_int(const struct device *dev)
|
|
{
|
|
return ll_func_is_active_alarm(RTC) != 0;
|
|
}
|
|
|
|
|
|
static uint32_t rtc_stm32_get_top_value(const struct device *dev)
|
|
{
|
|
const struct counter_config_info *info = dev->config;
|
|
|
|
return info->max_top_value;
|
|
}
|
|
|
|
|
|
static int rtc_stm32_set_top_value(const struct device *dev,
|
|
const struct counter_top_cfg *cfg)
|
|
{
|
|
const struct counter_config_info *info = dev->config;
|
|
|
|
if ((cfg->ticks != info->max_top_value) ||
|
|
!(cfg->flags & COUNTER_TOP_CFG_DONT_RESET)) {
|
|
return -ENOTSUP;
|
|
} else {
|
|
return 0;
|
|
}
|
|
|
|
|
|
}
|
|
|
|
void rtc_stm32_isr(const struct device *dev)
|
|
{
|
|
struct rtc_stm32_data *data = dev->data;
|
|
counter_alarm_callback_t alarm_callback = data->callback;
|
|
|
|
uint32_t now = rtc_stm32_read(dev);
|
|
|
|
if (ll_func_is_active_alarm(RTC) != 0
|
|
#ifdef CONFIG_COUNTER_RTC_STM32_SUBSECONDS
|
|
|| (data->irq_on_late && ll_func_isenabled_interrupt_alarm(RTC))
|
|
#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS */
|
|
) {
|
|
|
|
LL_RTC_DisableWriteProtection(RTC);
|
|
ll_func_clear_alarm_flag(RTC);
|
|
ll_func_disable_interrupt_alarm(RTC);
|
|
ll_func_disable_alarm(RTC);
|
|
LL_RTC_EnableWriteProtection(RTC);
|
|
#ifdef CONFIG_COUNTER_RTC_STM32_SUBSECONDS
|
|
data->irq_on_late = 0;
|
|
#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS */
|
|
|
|
if (alarm_callback != NULL) {
|
|
data->callback = NULL;
|
|
alarm_callback(dev, 0, now, data->user_data);
|
|
}
|
|
}
|
|
|
|
#if defined(CONFIG_SOC_SERIES_STM32H7X) && defined(CONFIG_CPU_CORTEX_M4)
|
|
LL_C2_EXTI_ClearFlag_0_31(RTC_EXTI_LINE);
|
|
#elif defined(CONFIG_SOC_SERIES_STM32C0X) \
|
|
|| defined(CONFIG_SOC_SERIES_STM32G0X) \
|
|
|| defined(CONFIG_SOC_SERIES_STM32L5X) \
|
|
|| defined(CONFIG_SOC_SERIES_STM32H5X)
|
|
LL_EXTI_ClearRisingFlag_0_31(RTC_EXTI_LINE);
|
|
#elif defined(CONFIG_SOC_SERIES_STM32U5X) || defined(CONFIG_SOC_SERIES_STM32WBAX)
|
|
/* in STM32U5 family RTC is not connected to EXTI */
|
|
#else
|
|
LL_EXTI_ClearFlag_0_31(RTC_EXTI_LINE);
|
|
#endif
|
|
}
|
|
|
|
|
|
static int rtc_stm32_init(const struct device *dev)
|
|
{
|
|
const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
|
|
const struct rtc_stm32_config *cfg = dev->config;
|
|
struct rtc_stm32_data *data = dev->data;
|
|
|
|
data->callback = NULL;
|
|
|
|
if (!device_is_ready(clk)) {
|
|
LOG_ERR("clock control device not ready");
|
|
return -ENODEV;
|
|
}
|
|
|
|
/* Enable RTC bus clock */
|
|
if (clock_control_on(clk, (clock_control_subsys_t) &cfg->pclken[0]) != 0) {
|
|
LOG_ERR("clock op failed\n");
|
|
return -EIO;
|
|
}
|
|
|
|
/* Enable Backup access */
|
|
z_stm32_hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
|
|
#if defined(PWR_CR_DBP) || defined(PWR_CR1_DBP) || \
|
|
defined(PWR_DBPCR_DBP) || defined(PWR_DBPR_DBP)
|
|
LL_PWR_EnableBkUpAccess();
|
|
#endif /* PWR_CR_DBP || PWR_CR1_DBP || PWR_DBPR_DBP */
|
|
|
|
/* Enable RTC clock source */
|
|
if (clock_control_configure(clk,
|
|
(clock_control_subsys_t) &cfg->pclken[1],
|
|
NULL) != 0) {
|
|
LOG_ERR("clock configure failed\n");
|
|
return -EIO;
|
|
}
|
|
|
|
#if !defined(CONFIG_SOC_SERIES_STM32WBAX)
|
|
LL_RCC_EnableRTC();
|
|
#endif
|
|
|
|
z_stm32_hsem_unlock(CFG_HW_RCC_SEMID);
|
|
|
|
#if !defined(CONFIG_COUNTER_RTC_STM32_SAVE_VALUE_BETWEEN_RESETS)
|
|
if (LL_RTC_DeInit(RTC) != SUCCESS) {
|
|
return -EIO;
|
|
}
|
|
#endif
|
|
|
|
if (LL_RTC_Init(RTC, ((LL_RTC_InitTypeDef *)
|
|
&cfg->ll_rtc_config)) != SUCCESS) {
|
|
return -EIO;
|
|
}
|
|
|
|
#ifdef RTC_CR_BYPSHAD
|
|
LL_RTC_DisableWriteProtection(RTC);
|
|
LL_RTC_EnableShadowRegBypass(RTC);
|
|
LL_RTC_EnableWriteProtection(RTC);
|
|
#endif /* RTC_CR_BYPSHAD */
|
|
|
|
#if defined(CONFIG_SOC_SERIES_STM32H7X) && defined(CONFIG_CPU_CORTEX_M4)
|
|
LL_C2_EXTI_EnableIT_0_31(RTC_EXTI_LINE);
|
|
LL_EXTI_EnableRisingTrig_0_31(RTC_EXTI_LINE);
|
|
#elif defined(CONFIG_SOC_SERIES_STM32U5X) || defined(CONFIG_SOC_SERIES_STM32WBAX)
|
|
/* in STM32U5 family RTC is not connected to EXTI */
|
|
#else
|
|
LL_EXTI_EnableIT_0_31(RTC_EXTI_LINE);
|
|
LL_EXTI_EnableRisingTrig_0_31(RTC_EXTI_LINE);
|
|
#endif
|
|
|
|
rtc_stm32_irq_config(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct rtc_stm32_data rtc_data;
|
|
|
|
static const struct stm32_pclken rtc_clk[] = STM32_DT_INST_CLOCKS(0);
|
|
|
|
static const struct rtc_stm32_config rtc_config = {
|
|
.counter_info = {
|
|
.max_top_value = UINT32_MAX,
|
|
#ifndef CONFIG_COUNTER_RTC_STM32_SUBSECONDS
|
|
/* freq = 1Hz for not subsec based driver */
|
|
.freq = RTCCLK_FREQ / ((RTC_ASYNCPRE + 1) * (RTC_SYNCPRE + 1)),
|
|
#else /* !CONFIG_COUNTER_RTC_STM32_SUBSECONDS */
|
|
.freq = RTCCLK_FREQ / (RTC_ASYNCPRE + 1),
|
|
#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS */
|
|
.flags = COUNTER_CONFIG_INFO_COUNT_UP,
|
|
.channels = 1,
|
|
},
|
|
.ll_rtc_config = {
|
|
.AsynchPrescaler = RTC_ASYNCPRE,
|
|
#if !defined(CONFIG_SOC_SERIES_STM32F1X)
|
|
.HourFormat = LL_RTC_HOURFORMAT_24HOUR,
|
|
.SynchPrescaler = RTC_SYNCPRE,
|
|
#else /* CONFIG_SOC_SERIES_STM32F1X */
|
|
.OutPutSource = LL_RTC_CALIB_OUTPUT_NONE,
|
|
#endif /* CONFIG_SOC_SERIES_STM32F1X */
|
|
},
|
|
.pclken = rtc_clk,
|
|
};
|
|
|
|
#ifdef CONFIG_PM_DEVICE
|
|
static int rtc_stm32_pm_action(const struct device *dev,
|
|
enum pm_device_action action)
|
|
{
|
|
const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
|
|
const struct rtc_stm32_config *cfg = dev->config;
|
|
|
|
switch (action) {
|
|
case PM_DEVICE_ACTION_RESUME:
|
|
/* Enable RTC bus clock */
|
|
if (clock_control_on(clk, (clock_control_subsys_t) &cfg->pclken[0]) != 0) {
|
|
LOG_ERR("clock op failed\n");
|
|
return -EIO;
|
|
}
|
|
break;
|
|
case PM_DEVICE_ACTION_SUSPEND:
|
|
break;
|
|
default:
|
|
return -ENOTSUP;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#endif /* CONFIG_PM_DEVICE */
|
|
|
|
static const struct counter_driver_api rtc_stm32_driver_api = {
|
|
.start = rtc_stm32_start,
|
|
.stop = rtc_stm32_stop,
|
|
.get_value = rtc_stm32_get_value,
|
|
#ifdef CONFIG_COUNTER_RTC_STM32_SUBSECONDS
|
|
.get_value_64 = rtc_stm32_get_value_64,
|
|
#endif /* CONFIG_COUNTER_RTC_STM32_SUBSECONDS */
|
|
.set_alarm = rtc_stm32_set_alarm,
|
|
.cancel_alarm = rtc_stm32_cancel_alarm,
|
|
.set_top_value = rtc_stm32_set_top_value,
|
|
.get_pending_int = rtc_stm32_get_pending_int,
|
|
.get_top_value = rtc_stm32_get_top_value,
|
|
};
|
|
|
|
PM_DEVICE_DT_INST_DEFINE(0, rtc_stm32_pm_action);
|
|
|
|
DEVICE_DT_INST_DEFINE(0, &rtc_stm32_init, PM_DEVICE_DT_INST_GET(0),
|
|
&rtc_data, &rtc_config, PRE_KERNEL_1,
|
|
CONFIG_COUNTER_INIT_PRIORITY, &rtc_stm32_driver_api);
|
|
|
|
static void rtc_stm32_irq_config(const struct device *dev)
|
|
{
|
|
IRQ_CONNECT(DT_INST_IRQN(0),
|
|
DT_INST_IRQ(0, priority),
|
|
rtc_stm32_isr, DEVICE_DT_INST_GET(0), 0);
|
|
irq_enable(DT_INST_IRQN(0));
|
|
}
|