332 lines
8.2 KiB
C
332 lines
8.2 KiB
C
/*
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* Copyright (c) 2019 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <device.h>
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#include <xtensa/xtruntime.h>
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#include <irq_nextlevel.h>
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#include <xtensa/hal.h>
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#include <init.h>
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#include "soc.h"
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#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(soc);
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static uint32_t ref_clk_freq;
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#define CAVS_INTC_NODE(n) DT_INST(n, intel_cavs_intc)
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void z_soc_irq_enable(uint32_t irq)
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{
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const struct device *dev_cavs, *dev_ictl;
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switch (XTENSA_IRQ_NUMBER(irq)) {
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case DT_IRQN(CAVS_INTC_NODE(0)):
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dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(0)));
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break;
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case DT_IRQN(CAVS_INTC_NODE(1)):
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dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(1)));
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break;
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case DT_IRQN(CAVS_INTC_NODE(2)):
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dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(2)));
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break;
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case DT_IRQN(CAVS_INTC_NODE(3)):
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dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(3)));
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break;
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default:
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/* regular interrupt */
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z_xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq));
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return;
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}
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if (!dev_cavs) {
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LOG_DBG("board: CAVS device binding failed");
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return;
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}
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/* If the control comes here it means the specified interrupt
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* is in either CAVS interrupt logic or DW interrupt controller
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*/
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z_xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq));
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switch (CAVS_IRQ_NUMBER(irq)) {
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case DW_ICTL_IRQ_CAVS_OFFSET:
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dev_ictl = device_get_binding(DT_LABEL(DT_INST(0, snps_designware_intc)));
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break;
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default:
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/* The source of the interrupt is in CAVS interrupt logic */
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irq_enable_next_level(dev_cavs, CAVS_IRQ_NUMBER(irq));
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return;
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}
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if (!dev_ictl) {
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LOG_DBG("board: DW intr_control device binding failed");
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return;
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}
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/* If the control comes here it means the specified interrupt
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* is in DW interrupt controller
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*/
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irq_enable_next_level(dev_cavs, CAVS_IRQ_NUMBER(irq));
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/* Manipulate the relevant bit in the interrupt controller
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* register as needed
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*/
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irq_enable_next_level(dev_ictl, INTR_CNTL_IRQ_NUM(irq));
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}
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void z_soc_irq_disable(uint32_t irq)
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{
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const struct device *dev_cavs, *dev_ictl;
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switch (XTENSA_IRQ_NUMBER(irq)) {
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case DT_IRQN(CAVS_INTC_NODE(0)):
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dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(0)));
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break;
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case DT_IRQN(CAVS_INTC_NODE(1)):
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dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(1)));
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break;
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case DT_IRQN(CAVS_INTC_NODE(2)):
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dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(2)));
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break;
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case DT_IRQN(CAVS_INTC_NODE(3)):
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dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(3)));
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break;
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default:
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/* regular interrupt */
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z_xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq));
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return;
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}
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if (!dev_cavs) {
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LOG_DBG("board: CAVS device binding failed");
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return;
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}
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/* If the control comes here it means the specified interrupt
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* is in either CAVS interrupt logic or DW interrupt controller
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*/
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switch (CAVS_IRQ_NUMBER(irq)) {
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case DW_ICTL_IRQ_CAVS_OFFSET:
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dev_ictl = device_get_binding(DT_LABEL(DT_INST(0, snps_designware_intc)));
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break;
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default:
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/* The source of the interrupt is in CAVS interrupt logic */
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irq_disable_next_level(dev_cavs, CAVS_IRQ_NUMBER(irq));
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/* Disable the parent IRQ if all children are disabled */
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if (!irq_is_enabled_next_level(dev_cavs)) {
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z_xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq));
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}
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return;
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}
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if (!dev_ictl) {
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LOG_DBG("board: DW intr_control device binding failed");
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return;
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}
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/* If the control comes here it means the specified interrupt
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* is in DW interrupt controller.
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* Manipulate the relevant bit in the interrupt controller
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* register as needed
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*/
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irq_disable_next_level(dev_ictl, INTR_CNTL_IRQ_NUM(irq));
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/* Disable the parent IRQ if all children are disabled */
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if (!irq_is_enabled_next_level(dev_ictl)) {
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irq_disable_next_level(dev_cavs, CAVS_IRQ_NUMBER(irq));
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if (!irq_is_enabled_next_level(dev_cavs)) {
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z_xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq));
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}
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}
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}
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int z_soc_irq_is_enabled(unsigned int irq)
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{
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const struct device *dev_cavs, *dev_ictl;
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int ret = -EINVAL;
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switch (XTENSA_IRQ_NUMBER(irq)) {
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case DT_IRQN(CAVS_INTC_NODE(0)):
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dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(0)));
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break;
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case DT_IRQN(CAVS_INTC_NODE(1)):
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dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(1)));
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break;
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case DT_IRQN(CAVS_INTC_NODE(2)):
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dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(2)));
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break;
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case DT_IRQN(CAVS_INTC_NODE(3)):
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dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(3)));
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break;
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default:
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/* regular interrupt */
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ret = z_xtensa_irq_is_enabled(XTENSA_IRQ_NUMBER(irq));
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goto out;
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}
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if (!dev_cavs) {
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LOG_DBG("board: CAVS device binding failed");
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ret = -ENODEV;
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goto out;
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}
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switch (CAVS_IRQ_NUMBER(irq)) {
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case DW_ICTL_IRQ_CAVS_OFFSET:
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dev_ictl = device_get_binding(DT_LABEL(DT_INST(0, snps_designware_intc)));
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break;
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default:
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/* The source of the interrupt is in CAVS interrupt logic */
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ret = irq_line_is_enabled_next_level(dev_cavs,
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CAVS_IRQ_NUMBER(irq));
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goto out;
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}
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if (!dev_ictl) {
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LOG_DBG("board: DW intr_control device binding failed");
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ret = -ENODEV;
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goto out;
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}
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ret = irq_line_is_enabled_next_level(dev_ictl, INTR_CNTL_IRQ_NUM(irq));
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out:
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return ret;
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}
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static inline void soc_set_resource_ownership(void)
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{
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volatile struct soc_resource_alloc_regs *regs =
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(volatile struct soc_resource_alloc_regs *)
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SOC_RESOURCE_ALLOC_REG_BASE;
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int index;
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/* set ownership of DMA controllers and channels */
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for (index = 0; index < SOC_NUM_LPGPDMAC; index++) {
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regs->lpgpdmacxo[index] = SOC_LPGPDMAC_OWNER_DSP;
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}
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/* set ownership of I2S and DMIC controllers */
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regs->dspiopo = SOC_DSPIOP_I2S_OWNSEL_DSP |
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SOC_DSPIOP_DMIC_OWNSEL_DSP;
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/* set ownership of timestamp and M/N dividers */
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regs->geno = SOC_GENO_TIMESTAMP_OWNER_DSP |
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SOC_GENO_MNDIV_OWNER_DSP;
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}
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uint32_t soc_get_ref_clk_freq(void)
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{
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return ref_clk_freq;
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}
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static inline void soc_set_audio_mclk(void)
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{
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#if (CONFIG_AUDIO)
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int mclk;
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volatile struct soc_mclk_control_regs *mclk_regs =
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(volatile struct soc_mclk_control_regs *)SOC_MCLK_DIV_CTRL_BASE;
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for (mclk = 0; mclk < SOC_NUM_MCLK_OUTPUTS; mclk++) {
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/*
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* set divider to bypass mode which makes MCLK output frequency
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* to be the same as referece clock frequency
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*/
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mclk_regs->mdivxr[mclk] = SOC_MDIVXR_SET_DIVIDER_BYPASS;
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mclk_regs->mdivctrl |= SOC_MDIVCTRL_MCLK_OUT_EN(mclk);
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}
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#endif
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}
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static inline void soc_set_dmic_power(void)
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{
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#if (CONFIG_AUDIO_INTEL_DMIC)
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volatile struct soc_dmic_shim_regs *dmic_shim_regs =
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(volatile struct soc_dmic_shim_regs *)SOC_DMIC_SHIM_REG_BASE;
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/* enable power */
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dmic_shim_regs->dmiclctl |= SOC_DMIC_SHIM_DMICLCTL_SPA;
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while ((dmic_shim_regs->dmiclctl & SOC_DMIC_SHIM_DMICLCTL_CPA) == 0U) {
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/* wait for power status */
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}
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#endif
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}
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static inline void soc_set_gna_power(void)
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{
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#if (CONFIG_INTEL_GNA)
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volatile struct soc_global_regs *regs =
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(volatile struct soc_global_regs *)SOC_S1000_GLB_CTRL_BASE;
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/* power on GNA block */
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regs->gna_power_control |= SOC_GNA_POWER_CONTROL_SPA;
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while ((regs->gna_power_control & SOC_GNA_POWER_CONTROL_CPA) == 0U) {
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/* wait for power status */
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}
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/* enable clock for GNA block */
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regs->gna_power_control |= SOC_GNA_POWER_CONTROL_CLK_EN;
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#endif
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}
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static inline void soc_set_power_and_clock(void)
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{
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volatile struct soc_dsp_shim_regs *dsp_shim_regs =
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(volatile struct soc_dsp_shim_regs *)SOC_DSP_SHIM_REG_BASE;
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dsp_shim_regs->clkctl |= SOC_CLKCTL_REQ_FAST_CLK |
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SOC_CLKCTL_OCS_FAST_CLK;
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dsp_shim_regs->pwrctl |= SOC_PWRCTL_DISABLE_PWR_GATING_DSP0;
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soc_set_dmic_power();
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soc_set_gna_power();
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soc_set_audio_mclk();
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}
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static inline void soc_read_bootstraps(void)
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{
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volatile struct soc_global_regs *regs =
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(volatile struct soc_global_regs *)SOC_S1000_GLB_CTRL_BASE;
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uint32_t bootstrap;
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bootstrap = regs->straps;
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bootstrap &= SOC_S1000_STRAP_REF_CLK;
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switch (bootstrap) {
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case SOC_S1000_STRAP_REF_CLK_19P2:
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ref_clk_freq = 19200000U;
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break;
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case SOC_S1000_STRAP_REF_CLK_24P576:
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ref_clk_freq = 24576000U;
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break;
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case SOC_S1000_STRAP_REF_CLK_38P4:
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default:
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ref_clk_freq = 38400000U;
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break;
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}
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}
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static int soc_init(const struct device *dev)
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{
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soc_read_bootstraps();
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LOG_INF("Reference clock frequency: %u Hz", ref_clk_freq);
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soc_set_resource_ownership();
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soc_set_power_and_clock();
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return 0;
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}
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SYS_INIT(soc_init, PRE_KERNEL_1, 99);
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