62 lines
1.3 KiB
ArmAsm
62 lines
1.3 KiB
ArmAsm
/*
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* Copyright (c) 2020 ITE Corporation. All Rights Reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* common interrupt management code for riscv SOCs supporting the riscv
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* privileged architecture specification
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*/
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#include <kernel_structs.h>
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#include <offsets.h>
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#include <toolchain.h>
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#include <linker/sections.h>
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#include <soc.h>
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/* exports */
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GTEXT(__soc_handle_irq)
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/*
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* SOC-specific function to handle pending IRQ number generating the interrupt.
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* Exception number is given as parameter via register a0.
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*/
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SECTION_FUNC(exception.other, __soc_handle_irq)
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/* Clear exception number from CSR mip register */
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li t1, 1
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sll t0, t1, a0
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csrrc t1, mip, t0
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move t2,ra
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call get_irq
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move ra,t2
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/* Return */
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jalr x0, ra
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/*
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* __soc_is_irq is defined as .weak to allow re-implementation by
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* SOCs that does not truely follow the riscv privilege specification.
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*/
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WTEXT(__soc_is_irq)
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/*
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* SOC-specific function to determine if the exception is the result of a
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* an interrupt or an exception
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* return 1 (interrupt) or 0 (exception)
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*
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*/
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SECTION_FUNC(exception.other, __soc_is_irq)
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/* Read mcause and check if interrupt bit is set */
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csrr t0, mcause
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li t1, SOC_MCAUSE_IRQ_MASK
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and t0, t0, t1
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/* If interrupt bit is not set, return with 0 */
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addi a0, x0, 0
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beqz t0, not_interrupt
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addi a0, a0, 1
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not_interrupt:
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/* return */
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jalr x0, ra
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