208 lines
7.1 KiB
C
208 lines
7.1 KiB
C
/*
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* Copyright (c) 2016 Cadence Design Systems, Inc.
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* RTOS-SPECIFIC INFORMATION FOR XTENSA RTOS ASSEMBLER SOURCES
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* (FreeRTOS Port)
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*
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* This header is the primary glue between generic Xtensa RTOS support
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* sources and a specific RTOS port for Xtensa. It contains definitions
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* and macros for use primarily by Xtensa assembly coded source files.
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*
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* Macros in this header map callouts from generic Xtensa files to specific
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* RTOS functions. It may also be included in C source files.
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*
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* Xtensa RTOS ports support all RTOS-compatible configurations of the Xtensa
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* architecture, using the Xtensa hardware abstraction layer (HAL) to deal
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* with configuration specifics.
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*
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* Should be included by all Xtensa generic and RTOS port-specific sources.
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*/
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#ifndef XTENSA_RTOS_H
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#define XTENSA_RTOS_H
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#ifdef __ASSEMBLER__
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#include <xtensa/coreasm.h>
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#else
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#include <xtensa/config/core.h>
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#endif
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#include <xtensa/corebits.h>
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#include <xtensa/config/system.h>
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#include <xtensa/simcall.h>
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/*
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* Convert Zephyr definitions to XTENSA definitions.
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*/
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#undef XT_SIMULATOR
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#undef XT_BOARD
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#ifdef CONFIG_SIMULATOR_XTENSA
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#define XT_SIMULATOR 1
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#else
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#define XT_BOARD 1
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#endif
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#ifdef CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
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#undef XT_CLOCK_FREQ
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#define XT_CLOCK_FREQ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
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#endif
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#ifndef XT_TIMER_INDEX
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#if defined configXT_TIMER_INDEX
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/* Index of hardware timer to be used */
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#define XT_TIMER_INDEX configXT_TIMER_INDEX
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#endif
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#endif
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#ifndef XT_INTEXC_HOOKS
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#if configXT_INTEXC_HOOKS
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#define XT_INTEXC_HOOKS 1 /* Enables exception hooks */
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#endif
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#endif
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#if (!XT_SIMULATOR) && (!XT_BOARD)
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#error Either XT_SIMULATOR or XT_BOARD must be defined.
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#endif
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/*
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* Name of RTOS (for messages).
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*/
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#define XT_RTOS_NAME Zephyr
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/*
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* Define for enabling RTOS specific code. Enable only one of below lines.
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*/
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#define XT_RTOS_IS_ZEPHYR_OS 1
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#undef XT_RTOS_IS_FREE_RTOS
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/*
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* Check some Xtensa configuration requirements and report error if not met.
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* Error messages can be customize to the RTOS port.
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*/
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#if !XCHAL_HAVE_XEA2
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#error "Zephyr/Xtensa requires XEA2 (exception architecture 2)."
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#endif
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/*
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* RTOS CALLOUT MACROS MAPPED TO RTOS PORT-SPECIFIC FUNCTIONS.
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*
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* Define callout macros used in generic Xtensa code to interact with the RTOS.
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* The macros are simply the function names for use in calls from assembler
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* code.
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* Some of these functions may call back to generic functions in
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* xtensa_context.h .
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*/
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/*
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* Inform RTOS of entry into an interrupt handler that will affect it.
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* Allows RTOS to manage switch to any system stack and count nesting level.
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* Called after minimal context has been saved, with interrupts disabled.
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* RTOS port can call0 _xt_context_save to save the rest of the context.
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* May only be called from assembly code by the 'call0' instruction.
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*/
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#define XT_RTOS_INT_ENTER _zxt_int_enter
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/*
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* Inform RTOS of completion of an interrupt handler, and give control to
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* RTOS to perform thread/task scheduling, switch back from any system stack
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* and restore the context, and return to the exit dispatcher saved in the
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* stack frame at XT_STK_EXIT. RTOS port can call0 _xt_context_restore
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* to save the context saved in XT_RTOS_INT_ENTER via _xt_context_save,
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* leaving only a minimal part of the context to be restored by the exit
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* dispatcher. This function does not return to the place it was called from.
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* May only be called from assembly code by the 'call0' instruction.
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*/
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#define XT_RTOS_INT_EXIT _zxt_int_exit
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/*
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* Inform RTOS of the occurrence of a tick timer interrupt.
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* If RTOS has no tick timer, leave XT_RTOS_TIMER_INT undefined.
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* May be coded in or called from C or assembly, per ABI conventions.
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* RTOS may optionally define XT_TICK_PER_SEC in its own way (eg. macro).
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*/
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#define XT_RTOS_TIMER_INT _zxt_timer_int
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#if CONFIG_TICKLESS_KERNEL
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#define XT_TICK_PER_SEC 1000
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#else
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#define XT_TICK_PER_SEC CONFIG_SYS_CLOCK_TICKS_PER_SEC
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#endif /* CONFIG_TICKLESS_KERNEL */
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/*
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* Return in a15 the base address of the co-processor state save area for the
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* thread that triggered a co-processor exception, or 0 if no thread was
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* running. The state save area is structured as defined in xtensa_context.h
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* and has size XT_CP_SIZE. Co-processor instructions should only be used in
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* thread code, never in interrupt handlers or the RTOS kernel. May only be
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* called from assembly code and by the 'call0' instruction. A result of 0
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* indicates an unrecoverable error.
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*
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* The implementation may use only a2-4, a15 (all other regs must be
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* preserved).
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*/
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#define XT_RTOS_CP_STATE _zxt_task_coproc_state
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/*
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* HOOKS TO DYNAMICALLY INSTALL INTERRUPT AND EXCEPTION HANDLERS PER LEVEL.
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*
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* This Xtensa RTOS port provides hooks for dynamically installing exception
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* and interrupt handlers to facilitate automated testing where each test case
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* can install its own handler for user exceptions and each interrupt priority
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* (level). This consists of an array of function pointers indexed by interrupt
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* priority, with index 0 being the user exception handler hook. Each entry in
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* the array is initially 0, and may be replaced by a function pointer of type
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* XT_INTEXC_HOOK. A handler may be uninstalled by installing 0.
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*
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* The handler for low and medium priority obeys ABI conventions so may be
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* coded in C. For the exception handler, the cause is the contents of the
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* EXCCAUSE reg, and the result is -1 if handled, else the cause (still needs
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* handling). For interrupt handlers, the cause is a mask of pending enabled
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* interrupts at that level, and the result is the same mask with the bits for
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* the handled interrupts cleared (those not cleared still need handling). This
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* allows a test case to either pre-handle or override the default handling for
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* the exception or interrupt level (see xtensa_vectors.S).
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*
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* High priority handlers (including NMI) must be coded in assembly, are always
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* called by 'call0' regardless of ABI, must preserve all registers except a0,
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* and must not use or modify the interrupted stack. The hook argument 'cause'
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* is not passed and the result is ignored, so as not to burden the caller
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* with saving and restoring a2 (it assumes only one interrupt per level - see
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* the discussion in high priority interrupts in xtensa_vectors.S). The handler
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* therefore should be coded to prototype 'void h(void)' even though it plugs
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* into an array of handlers of prototype 'unsigned h(unsigned)'.
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*
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* To enable interrupt/exception hooks, compile the RTOS with
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* '-DXT_INTEXC_HOOKS'.
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*/
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#define XT_INTEXC_HOOK_NUM (1 + XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI)
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#ifndef __ASSEMBLER__
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typedef unsigned int (*XT_INTEXC_HOOK)(unsigned int cause);
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extern volatile XT_INTEXC_HOOK _xt_intexc_hooks[XT_INTEXC_HOOK_NUM];
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#endif
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/*
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* CONVENIENCE INCLUSIONS.
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*
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* Ensures RTOS specific files need only include this one Xtensa-generic
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* header. These headers are included last so they can use the RTOS
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* definitions above.
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*/
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#include "xtensa_context.h"
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#ifdef XT_RTOS_TIMER_INT
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#include "xtensa_timer.h"
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#endif
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#endif /* XTENSA_RTOS_H */
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